Akeana RISC-V takes on the whole ARM IP range
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A US startup has emerged from stealth mode with a database that can generate RISC-V CPU cores across the entire performance range from microcontrollers to the data centre.
Akeana is looking to take on ARM directly with several families of RISC-V cores, memory management units, interrupt controllers and interconnect all generated from a single System Verilog database, including matrix engines and vector engines for AI accelerators.
“We are coming out of stealth with what we think is the only RISC-V processor with the range of cores equivalent to Neoverse,” said Rabin Sugumar, CEO of Akeana tells eeNews Europe. “We do think this is an industry breakthrough, we don’t think it has been done before with this range of cores from a single database.
The company has raised $100m from experienced chip investors Mayfield and Kleiner Perkins over the last three years and has 150 staff, half in the US and half in Asia.
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“We are a pure IP company,” says Sugumar. “The innovations are a very broad set of IP with a low opex so we are able to sustain the development at low opex so to be successful with a small market share.”
“For ARM or MIPS they have a separate team for each core so you have lots of teams. All of our cores come out of a highly configurable database with innovative ideas on how to do this, from small microcontrollers to [the equivalent of] a V2 Neoverse core. If there is a bug or timing issue we fix it once.”
The compiler is separate and not generated by the database, which is different from the approaches taken by Tensilica or Codasip. But the gcc-03 open source compiler is good enough says Sugumar.
“So we can cover ARM’s entire range with a small team,” he said. “The configurability is what makes it low opex but customers don’t want a configurable database they don’t know what to do with it.”
So Akeana has produced three series of RISC-V cores, and individual cores can be customised for particular applications.
The 100 Series: a line of highly configurable processors with 32bit RISC-V single thread cores that supports applications from embedded microcontrollers to edge gateways and personal computing devices.
The 1000 series processor line includes 64bit RISC-V cores and an MMU to support rich operating systems, while maintaining low power and requiring low die area. These processors support in-order or out-of-order pipelines, multi-threading, vector extension, hypervisor extension and other extensions that are part of recent and upcoming RISC-V profiles, as well as optional AI computation extensions, executing four threads per cycle.
The 5000 series provide higher performance 64bit 12 stage out of order processor cores with 512bit vector engines and 4 threads per cycle for laptops, data centres, and cloud infrastructure. These processors are compatible with the Akeana 1000 Series but with much higher single thread performance to take on the ARM X-series.
There are ten cores across the three families, although modifications can be made in a matter of weeks and are included in the database for other cores, he says.
The processor System IP: a collection of IP blocks needed for creation of processor SoCs, including a Coherent Cluster Cache, I/O MMU, and Interrupt Controller IPs. In addition, Akeana provides Scalable Mesh and Coherence Hub IP (compatible with AMBA CHI) to build large coherent compute subsystems for Data Centers and other use cases.
An AI Matrix computation engine offloads Matrix Multiply operations for AI acceleration. Configurable in size and supporting various data types and can be attached to the coherent cluster cache block like a core for optimal data sharing.
“We have the low end cores but the high end cores is where the money is and where the differentiation matters,” Bruno Putman VP of Sales & Development at Akeana tells eeNews Europe. “Right now the market for the really high end (Neoverse V2) cores is not there, but the market for Neoverse N1 and N2 [equivalent devices] is probably more interesting, more of a mobile play.”
The focus is on clusters of cores with the CHI and mesh interconnect for system on chip (SoC) designs to provide performance rather than chiplets. “Right now we are doing IP so if a customer comes to us and wants a chiplet we will consider that but that’s not come up but we do have integrated UCIe for chiplet protocols,” said Sugumar.
The company has three options for the IP for customers with a Akeana version of the Qemu emulator, the Cadence Palladium emulator, and they bring up the cores on FPGAs.
“We expect tapeouts later this year or next year, for small Android clusters for a wearable, networking applications where you need performance cores and multicore networking clusters, and AI where the in order cores with the vector extensions act as the AI engine,” said Sugumar.
The company is also starting a development for automotive certification.
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