Aldec strengthens support for VHDL and UVVM
Riviera-PRO 2019.10 users can now access newer attributes and improvements in the existing implementations of VHDL-2018, such as the to_string function and ‘IMAGE attribute can now be applied to all composite types that are representable.
The 2019.09.02 release of UVVM will feature new config to deassert tvalid once or multiple random times in AXI-Stream BFM and the ability to deassert tready multiple random times in AXI-Stream BFM.
Riviera-PRO’s Register Generator has also been enhanced to support FIFOs, indirect registers and arrays of registers.
More information
https://www.aldec.com/en/downloads/riviera-pro
Related news
FPGA-based NVMe data storage solution
Signal routing software picks a path for T&M switch system development
The anatomy of a network switch: an eight-port, gigabit glitch
Aldec optimizes FPGA routing resources for power and performance gains
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :