Algorithm speeds fault simulation for safety-relevant chip IP
The Optima Safety Platform (OSP), presented at the recent Design and Verification Conference (DVCon) in Munich, is based on Optima’s Fault Injection Engine, the core IP of the Israeli satrtup. According to the vendor, OSP is a next-generation fault analysis solution. It currently includes two automated tools: Optima-HE for hard error analysis and Optima-SE for soft error analysis. The company promises its users an order of magnitude increase in error analysis performance over today’s fastest solutions on the market. According to Optima founder and CEO Jamil Mazzawi, this slashes analysis time from months to days or even hours. This corresponds to an increase in performance by a factor of 1000, says Mazzawi. At the same time, higher coverage and design security can be achieved.
So far, the error analysis of large safety-critical devices in the automotive sector, as required by the ISO 26262 standard, can take months of computing time. If this time is reduced to a few days or hours, new forms of analysis can be used that drastically improve the safety and quality of the devices and at the same time allow the interference resistance to be evaluated. Optima’s automated CoverageMaximizer, currently under development, is expected to further improve the analysis process by increasing verification coverage and eliminating unconsidered design areas on the silicon.
Until now, only the traditional semiconductor industry fault simulation was available for the analysis of safety faults. This is a 30-year-old technique that was specially developed for testing in chip manufacturing. Optima has developed a new proprietary set of fault analysis algorithms specifically designed for injecting faults for safety analysis.
Using innovative parallel simulation and formal verification techniques, bypassing the historical legacy of manufacturing fault simulation and a new approach to fault optimization methods – pruning and collapsing fault lists – the Fault Injection Engine (FIE) achieves significantly improved analysis performance. A proprietary benchmark has shown that the FIE analyzes a commercial design more than 1000 times faster than a fault simulator. The used error simulator was considered to be the fastest of its kind.
Optima used the FIE technique as a basis to develop special solutions for different error scenarios. Optima-HE uses FIE and allows comprehensive error analysis of permanent errors. According to the ISO 26262 categorization, the solution identifies potentially dangerous errors in a design that are not caught by a safety mechanism and can cause significant failures with possible personal injury. Accelerating the analysis process to just a few days or hours allows development teams to predict an accurate measure of fault coverage as they need it for an ASIL-D assessment of their devices. In addition, Optima-HE includes CoverageMaximizer technology that identifies areas of the device that have not been sufficiently tested. It guides engineers in how to close these hard-to-find gaps in the process.
Optima-SE equally relied on FIE, but allows the analysis of transient errors. Transient errors are notoriously difficult to identify due to their transient nature. The flip-flop “hardening” technique is used to eliminate the effects of these transient defects in critical design areas. However, this hardening of each and every flip-flop of a design is associated to higher silicon area footprint and higher power consumption. In an iterative application of failure analysis, it is possible to identify a subset of the flip-flops throughout the design whose hardening results in high design immunity to transient failure. This allows the hardening effort to be limited to the required level. However, this approach requires many error analysis runs that would go beyond the scope of most development programs.
Optima-SE uses the FIE approach to reduce the time required for this process to a reasonable level, thus allowing a significant increase in device quality. Applying Optima-SE to a customer design of a commercially available CPU has shown that Optima-SE runs several orders of magnitude faster than normal RTL simulation.
Optima Design Automation describes itself as a pioneer in the field of failure analysis to ensure functional safety in the automotive industry. The company’s automated solutions target specific failure conditions, accelerate the failure simulation required by ISO 26262, and significantly increase analysis coverage and device quality. The company works with leading semiconductor manufacturers and EDA tool vendors to develop complete solutions that accelerate the time to market of safety-critical devices.
Related articles:
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Cadence memory IP certified for ISO 26262 ASIL C
A Developer’s View of ISO 26262
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