All-purpose hybrid DSP/controller architecture
As well as offering general purpose DSP capabilities for motor control and electrification, the new CEVA-BX architecture also targets the automotive and industrial markets, which are underserved by legacy DSPs or MPU/MCUs with low-performance DSP co-processing.
CEVA-BX combines the low power requirements of DSP kernels with the high-level programming and compact code size requirements of a large control code base. Using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at the TSMC 7nm process node using common standard cells and memory compilers. The CEVA-BX Instruction Set Architecture (ISA) supports Single Instruction Multiple Data (SIMD) widely used in neural network inference, noise reduction and echo cancellation, as well as half, single and double precision floating point units for high accuracy sensor fusion and positioning algorithms.
CEVA-BX employs a large orthogonal general purpose register set for maximum C compiler efficiency, Branch Target Buffer (BTB) for minimising branch overhead, hardware loop buffer for reduced power consumption of code loops, fully cached memory subsystem, and native support for all standard C types. Its CoreMark/MHz score of 4.5 reflects the control capabilities of the architecture. Customers can also add proprietary ISA into the architecture using CEVA-Xtend to accelerate proprietary algorithms and take advantage of CEVA’s automatic Queue and Buffer management mechanisms to integrate co-processors and create a cluster of CEVA-BX cores.
The CEVA-BX initially comes in two configurations – CEVA-BX1 with single 32X32-bit MAC and quad 16X16-bit MACs and CEVA-BX2 with quad 32X32-bit MACs and octal 16X16-bit MACs, that are also capable of supporting 16 x 8-bit and 8 x 8-bit MAC operations. CEVA-BX2 addresses intensive workloads such as 5G PHY control, multi-microphone beamforming and neural networks for speech recognition, with up to 16 GMACs per second.
The CEVA-BX family is accompanied by a comprehensive software development toolchain, including an advanced LLVM compiler, Eclipse-based debugger, DSP and neural network compute libraries, neural network frameworks support such as Android NN API, ARM NN, and Tensorflow Lite, and choice of RTOS.
More information
https://www.ceva-dsp.com/app/multipurpose-dsp-controller/
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