All systems go for 7nm FDSOI

All systems go for 7nm FDSOI

Interviews |
By Nick Flaherty

Cette publication existe aussi en Français

Nick Flaherty talks to Leti CEO Sébastien Dauvé and CTO Jean-René Lèquepeys at the Innovation Days this week on the FAMES pilot line, 6G, quantum and neuromorphic computing.

This week this seen the announcement of an  €830m pilot line in France for 10nm and 7nm FDSOI technology for next generation 5G and 6G chip and system designs

“We have two main challenges,” said Dauvé. “The velocity of the innovation from our partners which means you have to be rapid to find the right ideas and make the industrial transfers and that’s a major challenge and the other channel is on system sustainability

“We have our own clean room to experiment for the use of water, materials, energy and we help industry transform their processes and the main goal will be to help end users to change the use of their devices for example to be more modular, to reuse devices, this is a big, big area and we are sure we can play a role as we are connected to the entire ecosystem

It might seem strange that the new FAMES semiconductor pilot line in Grenoble, France, has five areas of focus, from materials to packaging. But the ultimate aim of €830m being spent on the virtual  line is to create the next generation of stacked 3D RF system devices for 5G and 6G.

CEA-Leti launches FAMES pilot line project

The line will develop the next generation of fully depleted silicon on insulator (FD SOI) process technology down to 10nm and 7nm for foundries such as GlobalFoundries and Samsung as well as chip makers such as Qualcomm and ST Microelectronics.

“The key market is 5G and 6G an in 6G we need new filters for 7 to 15GHz which is very promising and new chips are needed as there will be over 100 filters that need to be combined and could be put on top of the FDSOI transistors,” says CTO Lèquepeys.

The 10nm FD SOI process will have an aggressive frequency (Ft) of 450GHz, while the 7nm process is intended to reach 540GHz, he says.

“This will have the same performance as 5nm FinFET for pure digital and much better for Rf and analog,” he says, with a 64nm poly pitch and metal pitches of 48 and 40nm.

“With that,in the future we need to add non-volatile memories with different features for a wide spectrum of applications,” he said

“Its not a good way to go for monolithic solution for an SoC as we need to select the right technology for the right function. To do that we need heterogeneous integration to stack the chips with 3D heterogeneous and 3D monolithic  

“There are also constraints in power so we need the DC-DC converters with the tiny inductors. These will be separate in the first step but could be integrated. These can all be mixed together to create disruptive chip architectures,” he said.

For the line Leti is expanding its site with two additional clean rooms and equipment including an EUV lithography system, partly to accommodate the FAMES pilot line. This will be a virtual pilot line with equipment spread across multiple clean rooms on the site that are also used for other projects.

An ASML 300mm Twinscan 2050i   immersion lithography  was installed in December and part of the FAMES project will determine whether this can be used down to 7nm line widths on FD SOI process. The EUV lithography scanner is not expected to be installed until 2026.

“The R&D will end in 2028 but still be open to 2031 – it will open from April 2025 to Sep 2025 for the first contracts and they can develop their own IP, we keep the IP for the technology but for the final IC design our partners own their IP. This is a big thing,” said Lèquepeys.

FAMES is one of four pilot lines across Europe, and the development has been coordinated to make sure there is no significant competition or overlap.

The €830m funding comes half from the Chips Joint Undertaking and half from the member states, with the country hosting each line funding the majority. For Leti, this means 88% of the member state funding, or around €400m, just under half overall, is coming from the French government. This is repeated across Europe, with the sub-2nm line at imec backed by the Belgian government, the packaging line at Fraunhofer by Germany and the wide bandgap line at VTT by Finland. Poland and Spain in are also contributing to the FAMES pilot line, says Dauvé.

But i s not just about 5G and 6G wireless. FDSOI with adaptive back bias is also a key low power technology for quantum processors, and Leti is working with several different quantum technologies, including photonics.

“We have many bets including quantum and for us it is a really important part but we support other French and European startups exploring superconducting qubits and photonics  This is clearly a major ambition to be one of the first to find the right solution to scale up and industrialise as that will make the difference,” said Dauvé.

“We also have big bets on neuromorphic computing for AI and we are one of the most advanced research organisations in the world, last month we had 8 papers in Nature, and in parallel we are investigating how we can produce this technology so that it can become a reality.”

Leti s developing CryoCMOS technology to control the circuit with ECC error code correction. “We need a package dedicated working at cryotemperatures, that’s a big topic as well and CEA is working ono a way of programming a new computing engine with the full stack,” said CTO Lèquepeys.

Chasing integrated quantum chips with FD-SOI

FDSOI with ABB is essential for the ultra-low power devices that interface to the qubits, and Leti is working with its own spinout, Qoby, which will use the FAMES pilot line, but also with Paris-based Alice & Bob and C12QE as well as IQM in Finland and now France.

Lèquepeys doesn’t see Leti producing its own a quantum computer as a demonstrator. “We focus on the lower layer, and after that its up to the industrial companies. We need to go to the equivalent of the bios.”

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