Alphawave tapes out 112Gbps serdes on TSMC’s N3E process

Alphawave tapes out 112Gbps serdes on TSMC’s N3E process

Technology News |
By Peter Clarke

Data center chip and IP company Alphawave IP Group plc has announced the tape-out of its 1 to 112Gbps NRZ/PAM4 serializer/deserializer design on TSMC’s N3E 3nm process.

The design, called ZeusCORE100, is Alphawave’s most advanced multi-standard serializer/deserializer, supporting extra-long channels over 45dB and such data communications standards such as 800G Ethernet, OIF 112G-CEI, PCIe GEN6, and CXL3.0.

One thing that differentiates is the addition of a Most Likely Sequence Detector (MLSD) that extends channel reach performance. The MLSD uses Viterbi detection to make slicing decisions based on a sequence of data symbols. MLSD minimizes decision error across a sequence of symbols and improves the signal-to-noise ratio and bit error rate of systems.

“Alphawave is proud to be among the first to utilize TSMC’s most advanced 3nm technology,” said Tony Pialis, CEO of Alphawave, in a statement.

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