Altera aims for 3D chips with 14nm FPGAs
The ‘generation 10’ FPGAs will be built on both Intel’s 14nm tri-gate process for the Stratix 10 and TSMC’s 20nm process for the Arria 10 transceiver-based devices, with test chips on 14nm due later this year.
These follow the current Stratix 5 and Arria 5 families, with the Stratix 10 devices having ARM cores with clock rates of over 1GHz, twice the current clock rate. The process shift will also provide a potential power reduction of 70% at today’s performance levels and four times today’s logic density to 4m logic elements.
Altera has defined a high speed interface on the FPGA silicon to support other chips being mounted on the FPGA substrate using a silicon interposer. This is an internal specification that it will share with partners, says Danny Biran, senior vice president of corporate strategy at Altera.
This is aimed at adding DRAM and SRAM memory as well as customer ASICs in a single package. “We will make SRAM or buy DRAM and combine them,” said Biran. “If it’s an ASIC the customer will typically give us the ASIC and we will do the integration. The main value of the interface is to get higher performance with the memory bandwidth.”
Despite the move to Intel as a foundry, the Arria 10 transceiver-based devices will continue to be developed on the TSMC process says Biran. These will have 1.5GHz dual ARM Cortex-A9 processors with 28Gbps transceivers and DDR4 2666 interfaces and will sample in early 2014.
www.altera.com
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