Altera previews its “Generation 10” FPGAs and SoCs
Many of the upgrades in the new product lines – actual release dates for the two series of parts are not yet announced – are enabled by process changes. Arria 10 devices will – initially – be built in TSMC’s 20-nm planar transistor technology; Stratix 10 FPGAs and SoCs will use Intel’s 14 nm Tri-Gate process (Intel’s term for fin-fets) and an enhanced architecture.
Among the architectural changes are that, previously, Altera only included embedded processor cores in what it terms low- and mid-range programmable devices. Now, they will become available in high-end parts.
With recent generations of product, Altera says it has been able to keep advancing density figures, but progress in power/performance has slowed, for process reasons: now, the company says it has “broken out” of that limitation and is able to advance on both fronts. Stratic 10 will give you (relative to current Stratix parts) the same performance for 30% of the power: or twice the performance for 30% more power: or 40-60% more performance for today’s power levels. These trade-offs are based parameters you can set as a user, on a single device part number.
to deliver core performance two times higher than current high-end FPGAs, while enabling up to 70 percent power savings. Stratix 10 devices will run at up to 1 GHz clock speeds; they will also include transceivers that will signal (over very short distances, such as between die on a substrate, or between adjacent chips) at 56 Gbit/sec. Referring to these speeds, an Altera spokesman acknowledges, “That’s it: after this [anything faster] will have to be optical”. Stratix 10 chips will also offer over 10-times the DSP performance, with over 10 TeraFlops, of prior chips. They will include a “hard” processor core; the company will not say what it will be, but notes that, “Our agreement with Intel would allow us to build ARM cores on its [Intel’s] 14-nm TriGate process, “ adding cryptically, “but you should not read anything into that”. Stratix 10 will be “3-D capable” – actually, so-called 2.5-D, permitting logic dice to be mounted side-by-side on a passive silicon interposer to marry them memory and other sub-systems.
More immediate information is available on the Arria 10 family (though still limited details of release dates, as yet). The midrange programmable device family delivering both the performance and capabilities of current high-end FPGAs at the lowest midrange power, Altera says; up to 40% lower power compared to the previous family [or] at 15% higher performance. Arria 10 FPGAs and SoCs will have up to 1.15 million logic elements (LEs), integrated hard IP and a second-generation processor system that features a 1.5 GHz dual-core ARM Cortex-A9 processor. Arria 10 FPGAs and SoCs also provide 4-times greater bandwidth compared to the current generation, including 28-Gbps transceivers, and 3-times higher system performance, including 2666 Mbps DDR4 support and up to 15-Gbps Hybrid Memory Cube support. Altera declares support for the HMC concept, saying, “We believe it will become a standard”.
Generation 10 devices are supported by Altera’s Quartus II development software and tools for higher level design flows that include an OpenCL Software Development Kit (SDK), SoC Embedded Design Suite (EDS) and DSP Builder. This ldevelopment tool suite enables design teams to maximise productivity while making it easier for new design teams to adopt Generation 10 FPGAs and SoCs in their next-generation systems. The Quartus II software will continue to deliver the industry’s fastest compile times by providing Generation 10 FPGAs and SoCs an 8-times improvement in compile times versus previous generation. The substantial reduction in compile times is the result of leading-edge software algorithms that take advantage of modern multi-core computing technologies – that is, it derives from being able to use more compute resources effectively to run its code.
Early access customers are currently using the Quartus II software for development of Arria 10 FPGA and SoCs. Initial samples of Arria 10 devices will be available in early 2014. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and Quartus II software support for Stratix 10 FPGAs and SoCs in 2014.
Altera, www.altera.com/Gen10
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
