Altera schedules Stratix 10 FPGAs on Intel FinFET by year-end

Feature articles | June 8, 2015

By eeNews Europe

PLDs/FPGAs/ASICs

In an announcement – that was previously scheduled – which was issued immediately after the confirmation that Intel intends to acquire Altera, the FPGA maker disclosed further architectural and product details of its forthcoming Stratix 10 FPGAs and SoCs, the first samples of which will be available in late 2015. Altera had already told us that its, “next generation of high-end programmable logic devices delivering breakthrough levels of performance, integration, density and security,” would be built on Intel’s 14 nm Tri-Gate (finFET) process, and would include ‘hard’ ARM Cortex A53 cores in their “SoC” guise. This announcement fleshes out some of the detail, adds some performance points – that are derived largely from simulations, at this time – and clarifies the way that the most complex parts will be built on Intel’s technology. The latter aspect, Altera emphasises, was the result of the long-term cooperation between the two, and is not driven by the acquisition announcement.

The key points presented for Stratix 10 include a claimed 2x performance increase (clocks speed of the core FPGA fabric with “breakthrough power efficiencies”; a 3D integration structure based on Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology, that permits up to 5.5 million logic elements on a single, monolithic die; quad A53 cores that will clock at up to 1.5 GHz; and FPGA security capabilities via a Secure Device Manager. Altera asserts it has the, “highest performance, highest density FPGA with advanced embedded processing capabilities, GPU-class floating point computation performance and heterogeneous 3D SiP integration”.

Part of the performance gain derives from the “HyperFlex” architecture, which adds large numbers of registers throughout all core interconnect routing segments, enabling the design tools to carry out extensive register retiming, pipelining and other design optimisations. An Altera spokesman describes the resource as “[virtually] unlimited pipelining, for free.” Designers will be able to eliminate critical paths and routing delays, and more-rapidly close timing. Higher core logic performance also enables improvements in device utilisation and power by reducing the need for very wide data paths and other skew-inducing design constructs. Alter estimates the gains as enabling designs to operate with up to 70% lower power by reducing logic area requirements.

next page; 3D SiP technology

5.5 million logic elements on a single die is by far the highest available count, Altera says. By enabling high-bandwidth substrate connections, Intel’s EMIB technology permits serial interconnects (SERDES, etc.) to be located on separate dice around the core chip; that core die can therefore be all-fabric and the 5.5 million LE figure comes from using the largest reticle-size that the Intel process can manufacture. At that die size, defect density becomes an issue for yield and Altera adds that these chips will make use of its own redundancy technologies in the FPGA fabric. This is, the company adds, all-its-own-work and is not a native part of the Intel TriGate process. The EMIB structure – core fabric plus alternative peripheral functions co-located on a single high-performance substrate – allows Altera to limit the number of [expensive mask-set] core dice it builds while contemplating a wider range of functional devices. EMIB technology, Altera claims, provides higher performance, reduced complexity, lower cost and enhanced signal integrity compared to interposer-based approaches.

Initial Stratix 10 devices will use EMIB to integrate high-speed serial transceiver and protocol tiles with monolithic core logic. Implementing high-speed protocols and transceivers through a heterogeneous 3D SiP approach will allow Altera to rapidly deliver Stratix 10 device variants that address evolving market demands. For example, the use of heterogeneous 3D SiP integration provides Stratix 10 devices a path to support higher transceiver rates (56 Gbps), emerging modulation formats (PAM-4), communications standards (PCIe Gen4, Multi-Port Ethernet), and other capabilities such as analogue or high-bandwidth memory.

All densities in the Stratix 10 family will be available with an integrated 64-bit ARM quad-core Cortex-A53 hard processor system (HPS) with a full set of peripherals, including a system memory management unit, external memory controllers and high-speed communication interfaces.

Stratix 10 FPGAs and SoCs will base security capabilities around a Secure Design Manager (SDM) which delivers sector-based authentication and encryption, multi-factor authentication and physically unclonable function (PUF) technology. Altera has partnered with Athena Group and IntrinsicID on (respectively) encryption acceleration and PUF IP for Stratix 10 FPGAs and SoCs. This level of security makes Stratix 10 FPGAs and SoCs available for use in military, cloud security and IoT infrastructure, where multi-layered security and partitioned IP protection are paramount.

Altera’s Spectra-Q engine within the Quartus II software represents, a spokesman said, a “significant overhaul” of the core of Quartus II – in part, to exploit the HyperFlex architecture. Claims include up to 8X compile time improvements, versatile and fast-tracked design entry, drop-in IP integration, and support for OpenCL and other higher-level design flows.

Altera; www.altera.com/stratix10 and www.altera.com/hyperflex

next page… Specification listing, availability

Stratix 10 FPGA and SoC Technical Specifications:

• Up to 5.5 million logic elements in a monolithic die

• Heterogeneous 3D SiP integration combines FPGA fabric with high-speed transceivers

• Up to 144 transceivers deliver 4x serial bandwidth over the previous generation

• 64-bit quad-core ARM Cortex-A53 hard processor subsystem operating up to 1.5 GHz

• Hard floating point DSP enables single precision operations up to 10 TFLOPS throughput

• Secure Device Manager: Comprehensive high-performance FPGA security capabilities

• Industry-leading single-event upset (SEU) detection and scrubbing

• Footprint-compatible migration path from Arria® 10 FPGAs and SoCs

• Altera Enpirion power solutions offer maximum power efficiency and board area savings

• Intel 14 nm Tri-Gate process technology

Availability

Prospective users can get started on Stratix 10 designs immediately using the Fast Forward Compile performance evaluation tools. Engineering samples of Stratix 10 FPGAs and SoCs will be available in the fall of 2015. Embedded software developers can work with SoC virtual platforms from Mentor Graphics to accelerate Stratix 10 SoC embedded software development.