Altera slashes tool cost to drive system on chip FPGA developments

Altera slashes tool cost to drive system on chip FPGA developments

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By eeNews Europe

The cost of ARM’s DS-5 debug tool is $6000 per seat. The cost of the Altera specific version is just $1500.
“This is the first time that ARM has done a vendor specific tool kit,” said Chris Balough, Senior Director of Product Marketing for SoC Products at Altera. "

We have been very aggressive on making sure that no one is left out, with a processor dev kit with a fully featured board where you get all of these tools included."

Altera has started shipping samples of its first SoC FPGA, the largest, which combines two ARM A9 cores with 110,000 logic elements for around $50 to $60.

“We are now beginning to ship the first the largest of the Cyclone class and we have been surprised by how well we have seen market interest and design wins,” said Balough. “Perhaps we wanted to keep our expectations in check but the value proposition for this is where you have an FPGA and processor of a similar calibre, there’s more of that configuration than we realised and there’s a tremendous momentum in the ARM architecture.”
The DS-5 Altera Edition provides access to the two cores and to all the registers in peripheral blocks and embedded memory in the FPGA fabric. The data from across the system is time stamped and correlated in the tool. It supports ARM’s CoreSight debug protocol and SignalTap JTAG protocol so that soft peripheral such as an ARM Cortex M0+ core that are built in the FPGA fabric can also be debugged.
“This is the first silicon IC that implements the new CoreSight global timestamp capability so it is possible to go back as far as you want in the RTL waveforms and instructions with a common timebase,” he said.
“When you have 125Gbit/s bandwidth between the processing subsystem and the FPGA fabric over 4000 wires you can expect people to put memory mapped peripherals out in the FPGA,” said Balough. “Then you have a problem with debug as the debugger relies on the memory map. If the FPGA is changing all the time, how are you going to debug that? If you have hardware software interactions, how do you get these separate debug systems to work together? So we have connected the DS-5 and SignalTap together so that they can cross trigger and time correlate and we put all the plumbing in the silicon for these capabilities.”
The tool also includes ARM’s Streamline analysis tool that provides higher level details on core and kernel usage, memory access and power consumption.
“Many FPGA developers are going to use hardware acceleration blocks but they need software to benchmark whether this is having a positive effect and identify how many blocks they really need, so having tools that balance the CPU performance and resources is essential,” said Balough. “Streamline allows you to see software activity over time and correlate it with performance counters form the hardware and blocks in the FPGA. You can use this to find areas of optimisation. There is also a mode that displays the core allocation so you can see what Linux processes each core is running.”
However this is purely and analysis tool. “We let the developer make the decision on how to partition the code,” said Balough.
Altera is currently shipping initial samples of the largest Cyclone V SoC FPGA, the 5CSXA6. Broader sample availability will be in the first quarter of 2013, followed by production device availability later in the year.

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