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Altera to integrate Enpirion power interfaces into its FPGAs

Technology News |
By eeNews Europe

The first step following the acquisition is to use the power information from its Quartus tool to link to the Power SoC devices, says Danny Biran, senior vice president of strategy at Altera. “From the FPGA side part of the Quartus II software is a power estimator and depending on the design, usage, clock frequencies, use of the transceivers, it provides power requirement by voltage rail,” he said. “Now those power estimation results will link to a set of PSoCs as there will be one per rail.”
Integrating an interface is not so easy as it requires data from the IP blocks within the design which can come from customers. “We have been working with FPGAs for many years and there is definitely a loop that we have started to work on which will start to adjust the voltage depending on the chip design and the workload,” said Ashraf Lotfi, CEO and founder of Enpirion. “With the high switching frequency we have the control loop bandwidth is higher and that translates to a control loop that can respond to rapid changes in demand on load so we can see a communications link between the FPGA and PSoC for this,” he said. “That’s the grand vision of what can be done, but it can’t be done in cooperation between companies, it has to be done from the inside.”
“There are a number of standard protocols [for this communication loop] existing already,” said Biran. “Will we implement this in an IP block? Most probably the answer is yes,” he said. “We haven’t gone into that level of detail yet.”
The first step is to provide manufacturing data about the exact performance FPGA to the power management to allow the PSoC devices to optimize the speed or power consumption, says Biran.
www.altera.com


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