AMD launches cost optimised Xilinx FPGAs

New Products |
By Nick Flaherty

AMD has launched two Xilinx FPGAs optimised for cost in embedded applications.

The new designs of devices in the Artix and Zynq range are built on the same 16nm process as previous devices but use a different mix of resources to reduce power consumption. These will also have long availability for embedded designs.

“Devices are available of at least 15 year and its typically over 20 years and our devices are made for harsh environments rather than using temperature binning or screening,” said Chetan Khona, senor director for Industrial, Vision, Healthcare & Sciences at AMD.

The Artix UltraScale+ AU7P FPGA is the lowest density, lowest power, and most cost-optimized 12.5Gbps transceiver-based FPGA in the Artix  family portfolio. The new device provides up to 50% lower static power, 20% more I/O-to-logic ratio, and twice as many 3.3V HDIO compared to the AU10P device by flipping the architecture.

The static power calculation is based on scaling of the AU10P as an estimate of AU7P static power on Xilinx Power Estimator (XPE) tool version 2022.1.2 based on the logic cell count difference compared to AU7P.

The AU7P uses InFO fanout packaging to get a footprint of 8.5mm x 10.5mm for power-sensitive applications such as medical imaging, machine vision, professional cameras/monitors, and automotive radar/lidar.

The Zynq UltraScale+ ZU3T MPSoC is the smallest device in the family with 12.5Gbps GTH transceivers for cost-optimized applications. The GTH transceivers are configurable and tightly integrated with programmable logic resources in the FPGA rather than the ARM-based processor sub-system. This provides five times the transceiver bandwidth compared to other ZU3 device for networking applications, vision and video processing, and secured connectivity.

“The Zynq US+ ZU3T sits in the middle of the family and adds in features for high performance transceivers in the programmable logic,” said Khona. “All the Zynq devices have transceivers, some are tied to the processor subsystems so one of the new features is the lowest logic density with programmable logic-based transceivers. It’s aimed at smart city, indsitrial, AV broadcast, medical automotive with 157K cells, 5.1Mbits of block RAM and 14.0Mbit of UltraRAM – that really amplifies the memory ratio,” he added.

The AU7P device is expected to begin shipping pre-production and production silicon in the second half of 2023.The ZU3T device is expected to begin shipping pre-production silicon to early access customers in the first half of 2023, with production silicon expected in the second half of 2023.

AU7P and ZU3T devices will be available in automotive (XA) grade, qualified according to AEC-Q100 test specifications with full ISO26262 ASIL-C level certification.

Other articles on eeNews Europe



Linked Articles