ams’ ASIC design kit promises first-time-right designs in analogue 180nm CMOS
This release, a new version of its process design kit (PDK), features ams’ 180 nm CMOS speciality technology, which is now to be manufactured in ams’ 200 mm [wafer] fabrication facility in Austria. The PDK provides product developers with a plug-and-play tool set with improved analogue features and device performance as well as highly accurate simulation models. It facilitates first-time-right designs.
ams’ “hitkit” design environment comes with 1.8V and 5.0V NMOS and PMOS devices (substrate based, floating, low leakage and high threshold voltage options) and fully characterized passives including various capacitors. Area-optimized high-density and low-power digital libraries with gate densities up to 152 kGates/mm², updated digital and analogue I/O libraries with up to six metal layers as well as ESD protection cells with up to 8 kV HBM level are included. One-Time Programmable memories (OTP), online memory generation service for RAMs and ROMs as well as a Zero-Mask-Level-Adder EEPROM IP block (up to 8kbit) complete the offering.
Based on Virtuoso Custom IC technology 6.1.6 from Cadence, the new kit has highly accurate simulation models, extraction and verification run sets for both Calibre and Assura and flexible SKILL-based Pcells. The 180nm CMOS speciality process (“aC18”) is manufactured in ams’ fabrication facility in Austria, achieving very low defect densities and high yields.
The ams aC18 specialty process is suited for sensors and sensor interface devices in a wide variety of applications such as wearables, healthcare, home automation, smart cars and industry 4.0. It allows the development of innovative solutions for consumer electronics and industrial devices for the internet of things (IoT) and smart cities. Prototyping runs can be started immediately.
Volume production release is scheduled for July 2016. The new hitkit v4.14 is available now at https://asic.ams.com/hk414
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