AMS foundry shrinks 0.35-micron analog process
The analog low-noise process is dubbed A30 and has been created by an optical shrink by a factor of 0.9 from the AMS 0.35µm high-voltage CMOS process family. This shrink to 0.9 of linear dimensions implies 81 percent of the area consumed and a cost saving of approximate 19 percent cost saving in mass-production.
The A30 manufacturing process technology features isolated 3.3V NMOS and PMOS transistors, isolated 3.3V low threshold voltage devices, an isolated high voltage device with thin gate oxide (NMOSI20T), vertical bipolar transistors (VERTN1 and VERTPH) as well as an isolated 3.3V super-low noise transistor. This enables flicker noise reduction by a factor of between 4 and 10 for high drain currents compared to H35 process. Passive devices such as various capacitors and resistors complete the device offering.
The A30 process is suitable for sensing applications, analog read-out ICs in consumer electronics, automotive, medical and IoT devices. The process has been qualified in AMS’ 200mm wafer fab in Austria. The elements have been verified as 0.35-micron devices and then optically shrunk in the mask shop using completed GDSII data.
“Foundry customers benefit twice when using the A30 process for their complex ICs: our super low noise transistor with industry-benchmark flicker noise figures boost performance whereas the optical shrink notably reduces die area of noise sensitive applications,” said Markus Wuchse, general manager of the foundry division at AMS.
The A30 process is supported by hitkit v4.15 based on Virtuoso custom IC design suite from Cadence Design Systems Inc. The hitkit provides simulation models, and parameter extraction and verification run sets for both Calibre and Assura and flexible parameterized PCells.
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