An overview of the JESD204 standard for analog/digital converters
As the resolution and speed of converters has increased, the demand for a more efficient digital-side interface has grown. Currently, analog to digital converters (ADCs) are migrating from parallel LVDS (low-voltage differential signaling) and CMOS digital interfaces to a serialized interface called JESD204, developed by JEDEC (https://www.jedec.org/, formerly known as the Joint Electron Device Engineering Council, see https://www.jedec.org/about-jedec/jedec-history for historical background).
The JESD204 interface brings this efficiency while offering several advantages over its predecessors in terms of speed, size, and cost. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes, both of which make board designs much easier and offer lower costs in packaging and board designs.
The standard is also easily scalable so it can be adapted to meet future needs, as has been exhibited by the two revisions which the standard has already undergone. The JESD204 standard has had two revisions since its introduction in 2006 and is now at revision B.
As the standard has been adopted by converter vendors and users, it has been refined and new features have been added that have increased efficiency and ease of implementation. The standard applies to both analog to digital converters as well as digital to analog converters (DACs); however, the focus in this article will be on its application to ADCs.
In April of 2006, the original version of JESD204 was released. The standard describes a multi-gigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or ASIC. In this version, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver.
A graphical representation is provided in Figure 1. The lane shown is the physical interface between M number of converters and the receiver, where the interface consists of a differential pair of interconnects using current mode logic (CML). The link shown is the serialized data link that is established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.
Figure 1: JESD204 Original Standard
The lane data rate is defined between 312.5 Megabits per second (Mbps) and 3.125 Gigabits per second (Gbps) with both source and load impedance defined as 100 Ω ±20%. The differential voltage level is defined as being nominally 800 mV peak-to-peak with a common-mode voltage level range from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding which incorporates an embedded clock, removing the need to route an additional clock line, and the associated complexity of aligning an additional clock signal with the transmitted data at high data rates.
This form of serial data transmission allows the trace-to-trace tolerance to be relaxed, relative to synchronous-sampling parallel LVDS and CMOS interface designs. In addition, the encoding is DC balanced, which guarantees a significant transition frequency for use with clock and data recovery (CDR) designs.
The encoding also allows for the use of data and control characters which specify link alignment, maintenance, and monitoring. The standard specifies training patterns with these control characters that allow the lane to be aligned between the converter(s) and the receiver across the link.
The quality of the link is monitored in the receiver, and the link is established and dropped by the receiver based on certain error thresholds defined by the JESD204 standard. The standard was revised when proponents saw that it needed to incorporate support for multiple, aligned serial lanes with multiple converters, to accommodate increasing speeds and resolutions of converters.
In April of 2008, the first revision of the standard was released, designated JESD204A. This revision of the standard added the ability to support multiple aligned serial lanes with multiple converters. The lane data rates which it supported remained unchanged from the original version of the standard, from 312.5 Mbps up to 3.125 Gbps, and the frame clock also remained.
Increasing the capabilities of the standard to support multiple, aligned serial lanes made it possible for converters with high sample rates and high resolutions to meet the maximum supported data rate of 3.125 Gbps. Figure 2 shows a graphical representation of the additional capabilities added in the JESD204A revision to support multiple lanes.
Figure 2: First Revision – JESD204A
By adding these capabilities to the standard, converters with higher sample rates and/or higher resolutions could be supported. For example, a 14-bit ADC operating with a sample clock of 250 MHz would require an output data rate of 5.0 Gbps when transmitting over one link with one lane as described in JESD204.
However, with the revision to JESD204A, the standard now supported multiple aligned serial lanes and the converter samples could be mapped onto two aligned serial lanes. This would lower the data rate to 2.5 Gbps per lane, which is below the maximum supported data rate of 3.125 Gbps.
When dealing with an ADC, it is important to know the timing relationship between the sampled signal and its digital representation, in order to properly recreate the sampled signal in the analog domain once the signal has been received. Although both the original JESD204 standard and the revised JESD204A standard were higher performance than legacy interfaces, they were still lacking in one key element: deterministic latency in the serialized data on the link.
This timing relationship is affected by the latency of the ADC, which is defined as the number of clock cycles between the instant of the sampling edge of the input signal, until the time that its digital representation is present at the ADC’s outputs. In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the ADC and its serialized digital outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.
In July of 2011, the second and current revision of the standard was released, called JESD204B. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the supported data rates were pushed up to 12.5 Gbps, with different speed grades of devices being described.
This revision of the standard calls for a transition from using the frame clock as the main clock source, to using the device clock as the main clock source. Figure 3 is a representation of the additional capabilities added by the JESD204B revision.
Figure 3: Second (Current) Revision – JESD204B
In the previous two versions of the JESD204 standard, there were no provisions defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link re-synchronization events, the latency should be repeatable and deterministic.
This is accomplished by initiating the initial lane-alignment sequence in the converter(s) simultaneously across all lanes, at a well-defined moment in time by using an input signal called SYNC~. In addition, the receiver must have each lane of data buffered to account for skews across the serial data lanes. These buffers should be released simultaneously, also at a well-defined moment, in time by using a programmable number of cycles referred to as the Rx Buffer Delay (RBD).
In addition to the deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gbps, and divides devices into three different speed grades:
•The first speed grade aligns with the lane data rates from the JESD204 and JESD204A versions of the standard, and defines the electrical interface for lane data rates up to 3.125 Gbps. As mentioned earlier, the differential-voltage level for these data rates is nominally 800 mV peak-to-peak, with a common-mode voltage-level range from 0.72 V to 1.23 V (with both source and load impedance defined as 100 Ω ±20%).
•The second speed grade in JESD204B defines the electrical interface for lane data rates up to 6.375 Gbps. This speed grade is similar to the first speed grade, in that the differential voltage level is nominally 800 mV peak-to-peak. The common-mode voltage-level range has some slight differences based on the termination voltage specified at the receiver, but is generally similar to the first speed grade. The source and load impedance is the same, with both defined as 100 Ω ±20%.
•The third speed grade in JESD204B defines the electrical interface for lane data rates up to 12.5 Gbps. This speed grade lowers the differential voltage level required for the electrical interface to 400 mV peak-to-peak nominally, which effectively reduces the required levels by a factor of two when compared to the lower two speed grades. The common mode voltage level range is similar to the second speed grade and depends on the termination voltage specified at the receiver. Once again, both source and load impedance is defined as 100 Ω ±20%.
To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were usually the same.
This did not offer a lot of flexibility, and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives their respective device clock from a clock-generator circuit which is responsible for generating al device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.
As the speed and resolution of converters have increased, the demand for a more-efficient digital interface has increased. The JESD204 serialized data interface has been created to offer a better and faster way to transmit data from converters to receiver devices.
The interface has undergone two revisions to improve its implementation and meet the increasing demands brought on by higher-speed, higher-resolution converters. Each revision has answered the demands for improvements on its implementation, and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performance pushes higher, the JESD204 standard is poised to adapt and evolve to continue to meet the new design requirements necessary.
References (all are JEDEC Solid State Technology Association, https://www.jedec.org)
- JEDEC Standard JESD204 (April 2006)
- JEDEC Standard JESD204A (April 2008)
- JEDEC Standard JESD204B (July 2011)
About the author
Jonathan Harris is a product applications engineer in the high speed converter group at Analog Devices in Greensboro, NC. He has over seven years of experience as an applications engineer supporting products in the RF industry. Jonathan received his MSEE from Auburn University and his BSEE from UNC-Charlotte. In his spare time he enjoys mobile audio, nitro R/C, college football, and spending time with his two children.