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Analog Bits looks to 2nm power IP as it shows 3nm test chips

Analog Bits looks to 2nm power IP as it shows 3nm test chips

Technology News |
By Nick Flaherty



Analog Bits is demonstrating test chips for low drop out IP, power supply droop detectors and embedded clock LC PLL’s in TSMC N3P process as it develops 2nm designs.

This adds advanced 3nm to the Analog Bits IP on 4nm, 5nm, and automotive processes.

“Analog Bits continuous customer focus and passion for innovating IP’s to solve 3nm and 2nm design problems has enabled us to rapidly innovate and deploy IP’s to lower system costs and improve performance,” said Mahesh Tirupattur, Executive Vice President at Analog Bits, which is part of SemiFive.

“With SoC’s going multicores, managing power into the cores is imperative. We have designed novel LDO macros that can be easily scaled, arrayed and shared adjacent to CPU cores and simultaneously monitoring power supply health with our detector macros allowing customers to balance power real time. It is like PLL’s that maintain clocking stability we have are now able to offer IP’s to maintain power integrity in real time,” he said.

The company expanded its engineering capacity by opening its Prague Design Centre in February as part of the 2nm development. “Analog Bits has excelled in developing industry leading IP for our customers with best-in-class performance and power,” said Tirupattur.

“To do this, we have always hired talented Engineers who want to impact the world. We are excited to expand our capabilities that have been built over the last three decades to the enthusiastic, intelligent and passionate team in Prague. This milestone of expansion is strategic for our future growth and commitments to our customers.”

www.analogbits.com

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