Analog Bits moves IP to 5nm, targets 3nm
Analog Bits has ported its low-power mixed-signal IP to TSMC’s 5nm process technology and is moving to 3nm later this year.
The foundation IP includes precision clocking macros such as phase locked loops (PLLs) and digital locked loops (DLLs) as well as sensors, programmable interconnects such as multi-protocol SERDES and programmable IO.
The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our close collaboration with TSMC gives us the opportunity to help our mutual customers deliver the best possible reliability and quality to the end customers. We truly appreciate our years of strategic partnership with TSMC.”
The Analog Bits IP was a key part of the Cerberus wafer-scale AI processor for data centre applications. The second generation design integrated 850,000 processor cores in a single wafer. This was built on a 7nm process. The move to 5nm is vital for reducing the power consumption and increasing the performance. Analog Bits is working on a port of key IP including power management to TSMC’s 3nm process in Q3 this year
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