Analog EDA finally automated
Nevertheless, analog design automation tools that rival digital design automation tools are arriving on the scene. One approach is to use a design flow where traditional bottom-up techniques (standard cells) meet top-down automated optimization techniques according to professor Jurgen Scheible from the Robert Bosch Center Electronic Design Automation (EDA) division, at Reutlingen University (Germany).
Bosch has spent considerable funding the automation of analog design tools, the technology for which it transferred to Cadence Design Systems Inc. (San Jose, Calif.), according to Scheible.
"Design automation for analog circuits has not advanced anything like digital circuit automation," Scheible told us. "The extra work and costs of designing and producing analog layouts is a serious bottleneck in IC design."
The reason is that there are many more circuit types, each with many more parameters to be optimized, than in the typical digital circuit. Advances have been made for specific circuit types in recent years, according to Scheible, but much more needs to be done before analog can be said to have caught up with digital EDA. At the ISPD, Scheible introduced two techniques he has developed, which have since been transferred to Cadence, namely "continuous design flow" and "bottom-up meets top-down" design flows.
"A continuous layout design flow is a blind spot in today’s traditional analog flows," according to Scheible.
The typical design flow for analog circuits today is iteration, namely placement, routing and device generation, then repeat again and again until all the specifications of the circuit are met. Instead Scheible recommends a continuous design flow where first the engineer makes a symbolic preliminary layout, then makes is more and more detailed by adjusting actual physical parameters until it crystallizes into a physical design.
An alternative, is to use a bottom-up technique simultaneously with a top-down technique until they meed in the middle—an even more superior design flow for modern analog design, according to Scheible. However it suffers from a dilemma: the efficiency of top-down optimizing algorithms—measured by speed—are generally inversely proportional to the accuracy of the circuit.
To solve this problem, analog designers should begin with parameterized cells (PCells) which have already proven their merit in previous designs. By coordinating the bottom-up approach of physical layout designers (starting with PCells) with the top-down efforts of circuit designers adjusting PCell parameters, enables the two to more accurately meet in the middle and achieve an optimal design that meets the circuit’s specifications.
Analog designers Psyche
Professor Rob Rutenbar at the University of Illinois in Urbana described the reluctance of analog designers to adopt these automation methods starting with a history of analog design tools and culminating in the techniques described by Scheible above.
In the beginning there was only the open-source Simulation Program with Integrated Circuit Emphasis (Spice).
"Spice in-the-loop for simulation could take weeks to run, and the analytical modeling tools to increase accuracy could take months," Rutenbar told us. "Since then digital automation tools have solved these problems, but why is analog still not ‘solved’?"
According to Rutenbar, for analog, the things the EDA tools have gotten right since then are adding optimization automation, adding critical synthesis of IP (intellectual property), adding these and other tools embedded in the same design flows and adopting a divide-and-conquer methodology. What is missing, unfortunately, are accurate usage models of how real engineers do real layouts—in other words, automating the "secret sauce."
Optimization, constraint managers and statistical centering tools were automated early-on and well accepted by analog designers. However, analog engineers are still reluctant to use automated layout tools, because they have their own secret sauce for how a layout should be done.
"Engineers don’s want automated layout tools, because there is an aesthetic involved, that serves as a surrogate for correctness," Rutenbar told us. "Aesthetics of the layout is used for insurance that the circuit will work, because they have built similar circuits in the past that have proven to work well."
For the future, according to Rutenbar, engineers need to accept automated layout tools, especially for the future advanced node SoCs. For instance, today discrete analog circuits are cheap because they are using design rules that are up to five nodes behind the state-of-the-art in digital processes. However, for the future SoCs with mixed signal circuits on-chip, analog designers are going to have to learn how to create well performing analog functions at 14-, 10-, 7- and even 5-nanometers. They will also have to start making analog FinFETs. The biggest problems facing analog engineers using analog FinFETs, according to Rutenbar, are electromigration, signal and power routing that cause unacceptable DC voltage drops and self-heating of power circuits, all of which could be solved by using automated layout tools.
About the author:
R. Colin Johnson, Advanced Technology Editor, EE Times