Analog interface FMC module supports 5.4Gsps DAQ at 12-bits

Analog interface FMC module supports 5.4Gsps DAQ at 12-bits
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The LXD30K0 low latency, wide bandwidth analog interface FMC (FPGA Mezzanine Card) module from Logic-X is built around an ADC (EV12AS350A) and DAC (EV12DS460) from Europe’s Teledyne e2v for the analog input and output stages.
By Julien Happich


Well suited for electronic warfare systems, radar waveform generators and receivers and advanced digital radio frequency memory (DRFM) applications as well as medical and telecommunications systems, the module supports 5.4Gsps (Giga samples per second) data sampling at 12-bits resolution, which helps achieve a best-in-class signal-to-noise ratio (SNR). The unit features a low latency of 7.2ns on the analog input and a latency of just 1.2ns on the analog output. Additionally, the use of LVDS connectivity to the host carrier also facilitates an extremely low latency from the RF input to the RF output which can be less than 18ns depending on the carrier used.

The LXD30K0’s analog input stage also features a very wide bandwidth of 0.5MHz to 4.8GHz with sampling at 5.4Gsps generating an instantaneous bandwidth of 2.7GHz. The output bandwidth ranges from 0.5MHz to 6GHz and the instantaneous output bandwidth is 1.35GHz at a sampling data rate of 5.4Gsps. The inclusion of a flexible clock tree that generates a very clean, low jitter and low phase clock that is distributed to the ADC and DAC and external synchronization trigger input, ensures easy integration into single channel systems as well as standalone operation. For larger systems, it is possible to directly provide the sample clock to the front panel SSMC connector or to synchronize the local clock generator to an external reference clock.

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