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Analog IP for next gen 3nm technology

Analog IP for next gen 3nm technology

Technology News |
By Nick Flaherty



Analog Bits is demonstrating data for key analog IP on the next generation of  TSMC’s 3nm process technology, N3E.

The IPs include Wide Range PLL, PVT Sensor, Droop Detector, Bandgap, Crystal Oscillator pads and Clock Buffers. This development is part of a move to broaden the portfolio of analog foundation IPs on TSMC’s industry-leading process technologies. Multiple test-chips are planned and being executed to address broader markets of automotive, high performance computing and advanced chiplets.

“Analog Bits continues to lead in advanced mixed signal IP’s by collaborating with TSMC and our lead customers in advanced nodes such as N3E. In each generation we not only add more novelty to our IP offerings but we solve newer and technology centric problems for our customers” said Mahesh Tirupattur, Executive Vice President at Analog Bits.

“Power management in lower geometry has become an increasing concern, our new power sensors and regulators help diagnose and take mission critical corrective actions on advanced FinFET processes,” he said.

www.analogbits.com

 

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