Analog IP ported to GloFo’s 12nm FinFET process
The same circuits are available in the 12LP+ process intended for artificial intelligence (AI), cloud computing, and high-end consumer system-on-chips (SoCs).
The circuits include integer and Fractional Phase-Lock Loop (PLL), ring oscillator based PCIe 2/3 PLL, Process Voltage and Temperature (PVT) sensors, and Power on Reset (POR) circuitry and LC oscillator based PCIe 4/5 PLL for 12LP+.
“Globalfoundries has been a good partner for Analog Bits,” said Mahesh Tirupattur, executive vice president at Analog Bits, in a statement. “We are excited about the adoption and usage of our analog IP portfolio on GLOBALFOUNDRIES’ most advanced FinFET platform to address evolving AI requirements and the growing applications creating urgent demand for high-performance SoCs.”
Analog Bits’ integer/fractional, ultra-low jitter PLL is used in the Colossus Mk2 GC200 AI processor from Graphcore Ltd. on 7nm manufacturing process from TSMC. An integrated sensor for PVT and power supply monitoring in 7nm was used to ensure the device maintains the required thermal profile. The sensor also helps to ensure the integrity of the power delivery subsystem.
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