Analog synthesis remains remote

Analog synthesis remains remote

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By eeNews Europe

Today designers are facing increasing pressure to reduce design time and time-to-market. In the digital world, automation has long been used to enable turnaround of ever-larger designs in a reasonable timescale. Designers can estimate parasitics early in the design flow – at the RTL level – to see if they meet timing and power criteria. Thus design changes can be iterated relatively quickly until the design goals are met, with detailed layout following.


In the analog world, early estimation of parasitics has not been traditionally possible. Circuit simulation without parasitics extracted from real layout gets less and less useful in predicting performance as geometries have shrunk. Layout-dependent effects are difficult to estimate, and so the designer may have to wait days for the layout, and hence the parasitics, when layout is done manually. It requires an experienced analog layout engineer to take into account the matching of devices and the topologies required to give good performance, and they usually have only time to explore one layout topology. So the circuit design and layout are iterative. This is obviously not an ideal situation.


EDA companies have recently renewed efforts to bring automation to analog layout. So, for example, Helix from Ciranova (now Synopsys) and Modgens (from Cadence) are efforts to create more automation in the analog layout flow. The traditional digital philosophy of placing components, then routing them, has been found to be lacking, and existing tools are often called “analog prototyping” solutions. The problem lies in the fact that running placement without knowing the routing is difficult – the resulting placement may not be routable, or may not be dense enough.


New analog automation technology addresses this problem by considering the placement and routing as a single problem, a process known as PolyMorphic Layout. In fact, not just one solution is generated, but multiple layout topologies, each of which can be extracted and simulated to determine the optimal one to meet the required performance criteria. Pulsic’s Animate tool, for example, can generate more than 50 variants of layout for a PLL block in about a minute; the designer can then select several to extract and simulate and choose the best one to further refine.


Multiple layouts of a PLL generated automatically. Source: Pulsic.


The circuit designer can now very quickly try out different topologies, and experiment with different constraints in order to optimize the design. For example, the use of different guard ring structures or shielding can be tried in order to reduce unwanted noise coupling. The ability to save the constraints used to generate a particular layout means that iteration, if required, can be performed much more quickly, as can porting to new processes or PDKs.


Keith Sabine, product manager for analog solutions at Pulsic Ltd. (Bristol, England), has 35 years of experience in the semiconductor and EDA industries, starting out as a bipolar designer at Fairchild Semiconductor before moving into CMOS process development and characterization at Plessey Semiconductors. His EDA career has included time at Cadence, Simplex, Apache, and now Pulsic.


This article first appeared on EE Times’ Planet Analog website.


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