Analog tool qualified for Samsung 3nm
The move from 5nm to 3nm means using new transistor structures such as GAA rather than FinFET, which in turn means using different models, particularly for analog and mixed-signal (AMS) elements of a chip design, particularly embedded memory
The AFS tool was developed under Mentor Graphics and the Samsung Foundry certification for device models and design kits means designers can now verify early-stage AMS designs on the 3nm process. This process is intended to reduce total silicon size, use less power and improve performance over previous process nodes for analog, radio frequency (RF), mixed-signal, memory, and custom digital circuits. IT is expected to be in production in 2023.
More than 175 companies use the AFS Platform for circuit verification challenges, including high-speed I/Os, PLLs, ADCs/DACs, CMOS image sensors, RFICs, and embedded memory. analog design tools from Cadence Design Systems have also been qualified on the Samsung 3nm process.
The AFS tool is designed to provide SPICE accuracy 5x-10x faster than traditional SPICE tools and twice as fast as parallel SPICE simulators, says Siemens EDA. For large circuits the AFS Platform has a capacity of over 50m elements and 100m elements for for embedded memory and other array-based circuits.
“Samsung and Siemens have an established track record of collaboration to enable our mutual customers to fully leverage the AFS platform, and we are pleased that the AFS platform is now certified for early design starts on the very latest Samsung Foundry process,” said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics. “The combined expertise of Samsung Foundry and Siemens provides designers the ability to develop and quickly verify innovative ICs for a variety of high-growth markets and applications.”
Related 3nm articles
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- RUTHENIUM SHOWS WAY TO 2nm
- INTEL LOOKS TO SAMSUNG FOR CHIP MAKING
- SIEMENS EDA, ST TEAM ON CHIP PROCESS CHARACTERISATION
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