Analysis tool finds redundant silicon gates to boost performance
Axiomise in London, UK, has launched a fast area analysis tool for power, performance and area (PPA) optimisation in silicon chip designs.
The tool, called footprint, is vendor-neutral and provides an end-to-end analysis of a design to identify unused or underused components of silicon. Axiomise has developed an agile, interactive and user-centric interface for rapid refinement of the design model, starting with designs based on the RISC-V open instruction architecture.
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footprint works with any formal verification tool to generate reports on the power, performance and area utilization with techniques to improve the reachability and structural coverage of the design that synthesis tools cannot always clean out.
The tool finds redundant gates and registers that consume power but are never used. The area analyzer finds component-level granularity to precisely identify which design components never get used while still consuming power.
The tool has been tested on more than 80 designs, including processors, GPUs, communication IP and network-on-chip (NoC) interconnect.
“footprint is a key step in realizing our vision of making formal normal,” said Dr. Ashish Darbari, Founder and CEO of Axiomise. “This powerful tool provides architects and designers with a quick feedback loop during design bring-up, enabling them to exhaustively analyze silicon waste while optimizing for power and performance.”
Axiomise is planning to show footprint at the DVCon US 2025 conference in San Jose, California, on February 24th. For a limited time, footprint is available to try at no cost. Pricing is available upon request.
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