Analysis: TSMC ponders US wafer fab while awaiting trade rule changes

Analysis: TSMC ponders US wafer fab while awaiting trade rule changes

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By Peter Clarke

It is notable that the latest disclosure, that TSMC is “actively evaluating” a US fab plan, comes as the company is awaiting a final decision from the US on whether it wants to tighten rules on the export of products to China (see TSMC is planning a US wafer fab . . . again and Huawei stockpiling chips, expecting tighter US sanctions).

TSMC – rather like Taiwan itself – finds itself between a rock and hard place.

The majority of TSMC’s sales come from the broader fabless community which is led by US companies. But a significant part of the demand comes from China. TSMC does not want to offend China but ultimately the largest part of the market is outside China and will likely be led by US regulation. Similarly, the country is claimed by China but its independence from China is underwritten by the United States.

As such, economic actions in Taiwan and China can quickly become political. But these are rapids that TSMC has traditionally navigated with consummate skill. And mentioning the opportunity of putting a leading-edge or near leading-edge fab in the US sounds like interesting tack from TSMC.

TSMC is so successful at making leading-edge silicon it now is the global leader pulling clear of Samsung and having left Intel and Globalfoundries behind. In Globalfoundries case permanently, as that foundry has opted out of competing at 7nm and below. But China was responsible for about 20 percent of TSMC’s revenue in 2019. So, heightened export restrictions would be inconvenient for TSMC. They would effectively be a ban on sales of leading-edge silicon to China in general and to communications giant Huawei in particular. The latter is almost certainly the United States’ intent.

TSMC’s senior management was asked during the conference call to discuss 1Q20 financial results how they were managing the risk of such a ban. Chairman Mark Liu fielded the question saying: “We are now aware about the recent development of U.S. trade rule changes. However, these rule changes have – is still under draft.” He added: “And after the finalized draft, there will be another 30 days of grace period for the industry to respond. In general, we share the concerns, all the concerns of U.S. semiconductor communities such as voices from SEMI or from SIA.” (See Semiconductor industry pushes back against US export controls).

Liu added: “We have studied the various scenarios. And yes, there may be some near-term impact. And we will take – work with our customer dynamically and we will take appropriate measures so that to minimize the impact to TSMC. However, for the mid- to long-term, we think the underlying megatrend still holds.”

The megatrend that Liu refers to is TSMC’s need to maintain its capex at $15 billion to $16 billion in 2020 and roll out more capacity for 5G, smartphones and high-performance computing. And here comes the carrot: part of that roll out could be in the US although likely using budget in 2021 and later years.

It is notable that the last time TSMC mentioned the possibility of building a wafer fab in the US was in 2017 (see TSMC considers US for 3nm wafer fab site). That was shortly after the inauguration of President Donald Trump whose election campaign had included much talk about the need to bring jobs and investment to the US.

Foxconn Technology Group, Apple’s equipment assembly partner as TSMC is Apple’s application processor manufacturer, responded to that talk and agreed to build an LCD manufacturing plant in Wisconsin. However, three years on that project appears to have been in a constant state of re-appraisal and change and relatively little employment or manufacturing.

TSMC didn’t bite then and has been largely quiet on the matter since.

Next: $16 billion

Back in 2017 the prevailing wisdom was that a TSMC 3nm wafer fab would involve a lifetime spend of about $16 billion.

Chairman’s Liu’s observation on the call that the cost of establishing supply chain ecosystem is one of the issues, makes things somewhat easier. A state such as California or Oregon could easily find cash and some sort of supply chain consortium could be cobbled together to ease costs for TSMC for a project that would be in the supply chain’s and the state’s interest.

The second objection Liu mentioned is where to find the professional engineers to occupy one of TSMC’s leading-edge, highly automated wafer fabs. What about Oregon or Arizona?

That’s where Intel has some manufacturing that is struggling to keep up with TSMC. Intel even has its Fab42 shell in Chandler, Arizona, earmarked for 7nm production. Could some sort of deal be fashioned around that?

As Intel seeks to head up the supply chain and become a “solutions provider” rather than a chip provider, having a foundry partner close at hand could be one way forward.

Perhaps the question now is” will the US bite and defer a tightening of the regulations while TSMC can intensify its search for a wafer fab location and suitable subsidies to make starting up on a new campus economic?

Related links and articles:

News articles:

Huawei stockpiling chips, expecting tighter US sanctions

Semiconductor industry pushes back against US export controls

TSMC considers US for 3nm wafer fab site

TSMC next for New York fab?

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