Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version

Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version

Technology News |
By Nick Flaherty

Andes Technology has launched a safety-enhanced 32bit RISC-V CPU IP that it says is the first to be certified as fully compliant with ISO 26262 functional safety standards for the development of automotive applications

It is also planning a version with DSP extensions for higher performance early next year.

The AndesCore N25F-SE was assessed by SGS-TÜV Saar for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9. Andes says all the configurable options are also fully certified so that chip design teams are not limited by one fixed CPU configuration.

The 32bit RISC-V CPU core supports the standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size.

The 5-stage pipeline of the N25F-SE balances a high operating frequency and compact design while the flexible interfaces simplify SoC designs.

Following the N25F-SE, the D25F-SE with DSP/SIMD extension and Bit Manipulation extension is expected to be available in early 2023.

To enforce functional safety with a reasonable cost structure, proper safety measures for desired ASIL levels should be applied, from the least stringent ASIL A to the most stringent ASIL D. Examples of electronic systems where ASIL B is sufficient are dashboard, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS, and window control. Either to incorporate new electronic systems on board, or to upgrade existing ones without ISO 26262 compliance, the N25F-SE is well suited for the wide range of applications requiring ASIL B compliance.

The core helps reduce the cost and power consumption for SoCs requiring only an ASIL B processor IP without forcing them to use a double-sized dual-core lock-step solution with ASIL D. “As the only public RISC-V CPU IP company and a leader in the RISC-V ecosystem, we want to raise the awareness of the importance of ISO 26262 full compliance,” said Dr. Charlie Su, President and CTO of Andes Technology.

“Andes is the first RISC-V CPU vendor certified, for the development process of automotive processor cores, to be compliant with ISO 26262 standards up to ASIL D in 2020. With the certified development process in place, we formally started our functional safety roadmap to deliver at least one ISO 26262 compliant core every year to cover all segments of performance and features,” he said.

“Andes has developed a wide range of AndesCore processors, from driving cost sensitive MCUs to accelerating datacentre AI/ML computations. We are excited to announce our first safety-enhanced AndesCore the N25F-SE based on the most popular and mature CPU IP family, the 25-series,” he added.

The N25F-SE comes with the Safety Package which includes Safety manual, Safety analysis report (FMEDA and more), and Development Interface Outline. Together, the N25F-SE and its Safety Package reduces the time for SoC design teams to certify their ISO 26262 compliant SoCs.

This supported by development tools from Green Hills Software and IAR Systems.

“We are pleased to expand our production-ready automotive safety solutions to support the safety-certified AndesCore 25-Series RISC-V IP core family from the technology leader, Andes Technology,” said Dan Mender, Vice President, Business Development, Green Hills Software.

“This combined hardware-software solution for the AndesCore N25F-SE gives SoC providers a valuable head-start in offering integrated and optimized production-proven platforms for next-generation vehicle ECUs that require the highest performance and lowest power, with advanced tools that reduce their customers’ time to market and development costs.”

“RISC-V is being adopted at a remarkable speed in applications from the edge to the cloud and now it is entering the automotive market. IAR Systems support the mature and popular Andes RISC-V 25-series processors since its release a few years back in the IAR Embedded Workbench for RISC-V, Functional Safety edition. We are glad to learn that Andes N25F-SE has been certified for full ISO 26262 compliance,” said Rafael Taubinger, Sr. Product Marketing Manager at IAR Systems.

 “We are looking forward to extending our collaboration with Andes to support its Safety Enhanced processors starting from the N25F-SE enabling our mutual customers to speed up the path to using RISC-V in automotive safety-critical applications.”

The AndesCore N25F-SE is available for licensing now and Andes says more than six chip companies are already developing in-vehicle applications with the N25F-SE.  Renesas is a key partner using the Andes RISC-V cores for automotive chips.

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