Andes partners with EDA tool vendors for more RISC-V SoC support

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By eeNews Europe

Andes’ CPU IP can be found in over 2-Billion SoCs covering a wide range of applications, and the company has now adoped RISC-V as the subset of its fifth generation architecture, the AndeStar V5.

Based on the V5 architecture, Andes announced two high-performance 1+ GHz AndesCore processor IPs, the 32-bit N25 and the 64-bit NX25, both delivering over 2.8 DMIPS/MHz and over 3.4 CoreMark/MHz, and gate count as small as 30K and 50K, respectively, when using TSMC 28nm HPC process.

The N25 and NX25 are suitable for high-speed control tasks in networking, storage, and AI applications.

“To support the ever-increasing features of the emerging applications, SoC engineers face the challenges of the design complexity and time-to-market. They need powerful development tools such as fast system simulation for architectural exploration and SW development, emulation for functional verification and system validation, performance optimization, tough bugs tracing and embedded analytics. That is why Andes has worked with some of the partners on V3 AndesCore processors for many years,” Frankwell Jyh-Ming Lin, President of Andes Technology, commented, “We are now collaborating with Imperas, Lauterbach, Mentor, and UltraSoC to provide those advanced development tools for our new V5 AndesCore N25 and NX25, and the RISC-V community.”

About Imperas

Imperas –

Lauterbach –

Mentor Graphics –

UltraSoC –

Andes Technology –


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