Andes ships RISC-V vector IP for data centre transformer AI chips

Andes ships RISC-V vector IP for data centre transformer AI chips

Technology News |
By Nick Flaherty

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Andes Technology in Taiwan is shipping a high performance 64bit multicore RISC-V vector design that it developed for large language model datacentre AI chips.

The AX45MPV is the third generation of the AndesCore RISC-V vector processor series and can also be used for ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing.

Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019 leading to the AndesCore NX27V generating up to 4 512-bit vector (VLEN) results per cycle. Since then, RISC-V vector processor cores have become the choice for ML and AI chip designers.

The AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the previous AX45MP with the powerful vector processing unit inherited and enhanced from the NX27V to support six 1024bit vector instructions per cycle.

While the AX45MPV is essentially a Linux application processor with datacentre grade AI capabilities, the support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array.  

The dual-issue capability combined with up to six 1024-bit vector (VLEN) results per cycle in the AX45MPV can provide more than 3X performance comparing with its predecessor. This is supported by two 1024-bit memory interfaces and a new high-bandwidth vector local memory (HVM) option. This provides 1 or 2 HVM bank ports for vector loads/stores and an external DMA engine to move chunks of data in the background through an AXI-based HVM Access Port.

Computation tasks requiring an integrated coprocessor control along with data transfer can use the Andes Streaming Port (ASP) which, with HVM, doubles the memory bandwidth by, say, being able to load two vector data per cycle.

The AX45MPV also supports the latest ACE (Andes Custom Extension) that allows customers to create their own RISC-V styled vector instructions.  For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI. 

“Andes has been serving datacentre AI customers since 2019 with RISC-V Vector architecture and has accumulated rich experience. Equipped with the powerful 1024-bit vector unit, efficient support of multicore and Linux, and versatile configurations, the third generation of Andes vector processors AX45MPV is specially tailored for Large Language Models (LLMs). With the surge of generative AI applications in 2023, we see the AX45MPV taking the centre stage in AI and Machine Learning segments beyond the cloud,” said Dr. Charlie Su, President and CTO of Andes Technology.

Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. The advanced product package will come with Linux support and will be available in Q4 2023.

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