Anticipating a more virtual Moore’s law
“There will be another 30 years of growth for the semiconductor industry,” Lu predicted in an interview with EE Times. “We are going to see ‘effective’ 1nm. Moore’s Law will become a ‘virtual’ Moore’s Law.
The industry needs a boost. From 1995 to 2008, the sector delivered a 7 percent compound annual growth rate (CAGR) and a total return to shareholders nearly three times that of the overall stock market, management consultancy McKinsey notes in a 2015 report. Now, the story is much different.
Although some semiconductor players continue to thrive and gobble up smaller competitors, overall growth and revenue have declined.
The semiconductor industry can break out of stagnation at around $400 billion in annual revenue to achieve $1 trillion at 1nm, according to Lu. In his paper entitled “A New Silicon Way” that will be presented at the IEEE Asian Solid-State Circuits Conference on November 7 in Toyama, Japan, Lu outlines a transition to a new generation beyond the limitations of traditional linear scaling on silicon.
There is evidence that linear scaling has already reached its physical limits. “People say they are doing 10nm process modes, but you will not find any line widths at that level,” Lu says.
Departing Flatland
That’s why technology development has gone non-linear. In 2011, Intel announced its Tri-gate technology, leading the way from planar development of transistors on silicon into three dimensions. With 3D, even scaling by a factor of 0.85 results in a transistor density that is more like 0.5 scaling in two dimensions, Lu says.
Other companies have followed that trend. Toshiba built 3D NAND in 48 layers, and that memory has been used in Apple’s iPhone 7. Samsung has taken the idea a step further with the creation of a 64-layer flash memory device. The technology level was only 32nm, yet it was the virtual equivalent of 13nm, Lu notes.
“Now we are in silicon age 2.0 with vertical transistors and a scaling parameter of 0.8 to 0.85,” Lu says. “Silicon 3.0 is like a 3D landscape. We are seeing more and more people going there.”
Lu says that his theory, as described in his paper, starts with Silicon 4.0. The advances from the current 3.0 generation have enabled a lot of new applications such as augmented reality, virtual reality and machine intelligence, he says. The next threshold is what Lu calls heterogeneous integration, or the incorporation of silicon and non-silicon materials by means of technologies such as integrated fan out (InFO).
To InFO and Beyond
InFO is a packaging technology developed by Taiwan Semiconductor Manufacturing Co. (TSMC) to put bonding pads on the edge of silicon, eliminating the need for an interconnecting substrate. InFO provides a 20% reduction in package thickness, a 20% speed gain and 10% better thermal performance.
Infineon developed the technology in 2008 as embedded wafer-level ball grid array (eWLB,) to cut cost and package thickness while boosting component integration. However, yield problems impeded adoption of the new technology up until TSMC’s commercialization of InFO.
“This new InFO structure is what will lead heterogeneous integration to Silicon 4.0,” Lu says. “Another innovation is through interconnect via (TIV), which is like a pillar connecting the die to the outside. So you have both horizontal and vertical interconnect, both outside the silicon. That’s key for the continuation of heterogeneous integration. In the past, we couldn’t do TIV because we didn’t have InFO technology.”
With InFO, silicon will connect directly with parts such as lenses, sensors or actuators that are currently built into systems and haven’t yet been miniaturized, according to Lu.
“That’s heterogeneous integration of silicon and non-silicon using InFO,” Lu says. “All of these parts today are sitting on a printed circuit board, burning a lot of power. We are still five orders of magnitude away from optimal power consumption.”
That’s where Lu sees new potential for foundries, silicon designers and system houses to cooperate. Silicon is a $300 billion industry, but consumer electronics is a $1.6 trillion industry, he notes.
System makers will need heterogeneous integration to create smaller devices with lower power consumption, according to Lu.
“There should be a very smooth transition to these new technologies because we are still two generations away from the end of Moore’s Law,” Lu says. “Tri-gate, 3D NAND and InFO have come very smoothly. Silicon will scale down to 5nm with performance like 1nm.”
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