Application targeted, high-end FPGAs half power consumption and reduce cost
Speedster22i devices claim to be the first to include fully integrated hard IP protocol functions targeted for communications applications. The hard IP in Speedster22i devices includes the entire I/O protocol stack for 10/40/100 Gigabit Ethernet, Interlaken, PCI Express Gen 1/2/3 and memory controllers for 2.133 Gbps DDR3. In other FPGAs, these functions are implemented in the programmable fabric which consumes up to 500,000 equivalent look-up-tables (LUTs), makes timing closure difficult, and increases the cost and power consumption of the FPGA. Additionally, the embedded hard IP in Speedster22i FPGAs eliminate the cost of purchasing, integrating and testing these functions as soft IP.
“The combination of Intel’s 22-nm process leadership and our innovation in both the core fabric and embedded hard IP for targeted applications means that our customers will have a high‑end FPGA solution that is half the power and half the cost of competing FPGAs,” said Robert Blake, Achronix’s President and CEO.
“Part of our differentiating strategy is to integrate best-in-class, silicon-proven IP,” said John Lofton Holt, Achronix’s founder and Chairman of the Board. “For example, beyond the dramatic power and performance advantages afforded by Intel’s 22-nm process, our Speedster22i devices also leverage an entire portfolio of industry-leading I/O, core and packaging IP that was developed by Intel. This helped us achieve previously unreachable levels of performance and signal integrity, and at the same time, reduce our development time and development costs.”
Two families for different target applications
Speedster22i has two product families, high density (HD) and high performance (HP) that share the same I/O functionality and hard IP, and will be built on Intel’s 22-nm process featuring 3-D Tri-Gate transistors. Both families leverage the Achronix CAD Environment (ACE) design platform, which provides a seamless and familiar tool environment for designers.
HD Family: The HD FPGAs are a synchronous based family that offers the combination of the highest density FPGA with the lowest power consumption. There are 4 members in the HD family with the largest device having 1.7 million effective LUTs and 144 Mb of embedded RAM. Additionally, with up to sixteen 28-Gbps SerDes, sixty-four 12.75-Gbps SerDes and 960 general purpose 2.133-Gbps I/O, the HD family offers the industry’s highest I/O bandwidth, which is critical for high-end switch and bridging applications.
HP Family: The HP FPGAs use Achronix’s patented picoPIPE® self-timed architecture, operate at up to 1.5 GHz and are 3x to 4x faster than synchronous FPGAs. Speedster22i HP FPGAs are designed to achieve maximum performance for feed-forward data flow and DSP applications. The largest member of the HP family has 250 thousand LUTs and 64 megabits of embedded RAM.
Power advantage
For the communications target applications, the embedded hard IP consumes up to 90% less power than implementing the same functionality in the programmable fabric of general purpose FPGAs. Additionally, Intel’s advanced 22-nm 3-D transistors consume 50% less power and are nearly 40% faster than transistors built on 28-nm planar processes. For the HD devices, these combined factors result in up to 50% less total power consumption than mainstream FPGAs.
Robust 4th generation design tools
Both the HD and HP families are supported in Achronix’s mature and easy-to-use ACE design tools version 4.2 which are available now. The ACE design tools are built on the industry standard Eclipse Foundation open source platform and run under both Windows and Linux operating systems. Additionally, Achronix provides HDL Synthesis tools from both Synopsys and Mentor Graphics as part of the ACE tool suite.
Steve Mensor, Achronix’s Vice President of Marketing comments, “Our robust ACE design tools are now in their fourth generation and combined with the Speedster22i core performance advantage and embedded hard IP, typically makes timing closure a push-button operation.”
Achronix is focused on the success of its customers and has an early access program to help customers learn the ACE design tools and complete their designs. This program includes evaluation boards, onsite training and technical support. Customers should contact Achronix to obtain more information about the early access program.
Engineering samples of the HD1000 will begin shipping in Q3 2012. The HD1000 claims to be the industry’s largest FPGA with over 1 million effective LUTs and 84 Mb of embedded RAM. The remaining HD and HP devices will be rolled out in the following 12 months.
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