Applied Materials and A*STAR’s Institute of Microelectronics open joint 3D chip packaging R&D lab
The world-class facility features a 14,000 square foot Class-10 cleanroom and is equipped with a fully-integrated line of 300 millimetre manufacturing systems to support the research and development of 3D chip packaging, a critical growth area for the semiconductor industry.
The Centre is aimed to be the most advanced lab of its kind dedicated to wafer level packaging and will combine Applied Materials’ leading-edge equipment and process technology with IME’s leading research capability in 3D chip packaging. The Centre positions Singapore as a global leader in semiconductor R&D and is expected to help accelerate the development and adoption of 3D packaging technology globally.
Traditionally, chips are connected to packages using wires attached to only their edges. This approach limits the possible number of connections from the chip and the long wire connections result in signal speed delays and power inefficiencies. With 3D chip packaging, multiple chips can be stacked on top of each other and connected with wiring that runs vertically through the stack – called through-silicon vias (TSVs). When used to stack memory chips on logic chips, this technology is expected to reduce package size by 35%, decrease power consumption by 50%, and increase data bandwidth by a factor of eight or more times.
Conceived to support research collaboration between Applied Materials and IME, the Centre will also allow both parties to pursue independent research initiatives including process engineering, integration and hardware development. For Applied Materials, this is a significant addition of new capabilities in Singapore. The Centre also serves as a demonstration of how A*STAR is able to develop and nurture a local ecosystem for advanced R&D through partnerships with leading corporations. Research activities are already underway with a team of over 50 personnel.
Visit Applied Materials at www.appliedmaterials.com