Applied Materials pushes chiplet tech

Applied Materials pushes chiplet tech

Technology News |
By Nick Flaherty

Applied Materials is looking to take on its European semiconductor equipment rivals with new systems for integrating chiplets into advanced 2.5D and 3D packages.

Applied is already the largest supplier of technologies for hybrid integration with optimized chiplet systems spanning etch, physical vapor deposition (PVD), chemical vapour deposition (CVD), electroplating, chemical mechanical polishing (CMP), annealing and surface treatments.

It is now extending its chiplet system for hybrid bonding with silicon nitride (SiCN) and enhancing its through silicon via (TSVs) process technology to take on other equipment suppliers.

Chip-to-wafer and wafer-to-wafer hybrid bonding can be used to connect chiplets using direct, copper-to-copper bonds that enable the combined elements to perform as one. Hybrid bonding is the industry’s most advanced technology in production today, improving throughput and power by packing more wiring into smaller spaces and reducing the distances signals need to travel.

The Insepra SiCN deposition system a new silicon carbon nitride (SiCN) material that delivers the highest dielectric bonding strength in the industry and offers superior copper diffusion barrier properties. The stronger dielectric bonds give designers the structural stability needed to integrate far more copper-to-copper interconnects in a given area, which lowers power consumption and increases device performance.

The Catalys CMP solution helps customers control the amount of “dishing,” the intentional recessing of copper material on two surfaces that will be bonded in a subsequent high-temperature annealing step. CMP dishing can create unwanted metal loss at the top surfaces of the copper pads, which can cause air gaps that decrease the fidelity and strength of the copper-to-copper bonds. This uses a dynamic temperature control technique that reduces dishing and increases throughput.

TSVs are formed by etching trenches into silicon and then filling them with insulating liners and metal wires. As designers continue to integrate more logic, memory and specialty chips into advanced 2.5D and 3D packages, the number of TSV interconnects has expanded from a few hundred per package to thousands. To integrate more interconnects and accommodate taller stacks of chips, designers need the vias to become increasingly narrow and tall, which results in deposition uniformity variations that degrade performance and increase resistance and power consumption.

The Producer InVia 2 CVD System is a new CVD process that makes dielectric liners uniform and electrically robust at the extreme aspect ratios needed by logic and memory customers in a growing variety of TSV applications. The InVia 2 system uses a propriety in-situ deposition process which enables excellent conformality for high-aspect-ratio TSVs. The system also offers higher throughput than ALD technologies, thereby reducing the per-wafer cost of TSV to help further expand its adoption.

The Endura Ventura 2 PVD System extends its widely adopted predecessor to TSV applications with aspect ratios of up to 20:1. The Ventura 2 system increases the control of metal TSV wire deposition to ensure a complete fill that delivers high electrical performance and reliability.

The TSV PVD process has been co-optimized for use with the Produce InVia 2 CVD process and is being deployed by all advanced foundry/logic chipmakers and all major DRAM producers.

The latest generation of Applied’s Producer Avila PECVD System is designed for TSV reveal applications where wafers are bonded to temporary glass or silicon carriers and then thinned using CMP and etching to make the TSVs accessible for hybrid chiplet integration.

Following the TSV reveal steps, plasma-enhanced CVD technology is used to deposit a thin dielectric layer that electrically isolates the TSVs from each other. If the PECVD process generates heat above approximately 200 C, the delicate temporary bonding adhesive can be damaged, resulting in costly wafer yield loss.


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