Applied offers upgrades to support GAA transistors

Applied offers upgrades to support GAA transistors

Technology News |
By Peter Clarke

Applied Materials Inc. (Santa Clara, Calif.) has introduced Stensar chemical vapor deposition (CVD) as a way to further 2D scaling with EUV lithography and to support gate-all-around transistor formation. Stensar is being offered as an alternative to spin-on patterning films.

The 3D techniques include backside power distribution networks and gate-all-around (GAA) transistors – as a refinement of FinFETs. These are expected to make a major contribution to continued increases in logic density as 2D scaling slows.

The trade-off space that Applied addresses is becoming more complex and is now described by the acronym PPACt standing for power, performance, area, cost and time-to-market.

Due to the nature EUV resist, chip patterns need to be etched through a series of intermediate layers – called the transfer layer and hardmask – before they are finally etched into the wafer. Until now, these layers have been deposited using spin-on technology.


Applied is introducing the Stensar advanced patterning film for EUV which is deposited using Applied’s CVD system. Compared to spin-on deposition, Applied’s CVD film helps customers tune the EUV hardmask layers for specific thicknesses and etch resiliency so they can optimise for EUV pattern transfer uniformity across the entire wafer.

Applied has also announced the capability of Sym3 etch systems to etch and deposit materials in the same chambers to help improve EUV patterns before they are etched into the wafer. The Sym3 chambers gently remove EUV resist materials and then redeposit material in a special way that averages out the pattern variability caused by ‘stochastic errors’, Applied said. The improved EUV patterns increase yields and improve chip power and performance. As a result, Applied’s Sym3 technology is quickly growing beyond memory to foundry-logic.

Applied has also demonstrated how its PROVision® eBeam metrology technology can be used to see deeply within multilayer chips to precisely measure EUV-patterned features across the entire wafer, helping customers solve “edge-placement errors” that other metrology techniques cannot diagnose. Applied nearly doubled its eBeam system revenue in 2021 and has become the number-one supplier of eBeam technology.

Integrated materials system

Finally Applied has developed an IMS (Integrated Materials Solution) system for laying down the gate oxide stack. Thin gate oxides are required for GAA transistors but not at the cost of higher leakage current that wastes power and creates heat.

Applied’s new IMS system integrates atomic layer deposition (ALD), thermal steps, plasma treatment steps and metrology in a single, high-vacuum system. It reduces equivalent oxide thickness by 1.5 angstroms, enabling designers to increase performance with no increase in gate leakage or keep performance constant and reduce gate leakage by more than 10X, Applied claimed.

Applied is also demonstrating an IMS system for engineering GAA metal gate stacks, enabling customers to vary gate thicknesses in order to tune transistor threshold voltages to meet the performance-per-watt goals of specific computing applications ranging from battery-powered mobile devices to high-performance servers. It performs the high-precision metal ALD steps in high vacuum to prevent atmospheric contamination.

“Applied’s strategy is to be the PPACt enablement company for our customers, and today we are presenting seven innovations designed to enable customers to continue 2D scaling with EUV,” said Prabu Raja, general manager of the semiconductor products group at Applied Materials. “We are also detailing how GAA transistors will be manufactured in fundamentally different ways than today’s FinFET transistors.”

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