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Applied talks technologies, collaborations to aid chiplet assembly

Applied talks technologies, collaborations to aid chiplet assembly

Technology News |
By Peter Clarke



These are die-to-wafer hybrid bonding, wafer-to-wafer bonding and the introduction of novel advanced substrates. Applied is combining advanced packaging technologies and large-area substrates with industry collaborations to aid their adoption.

Heterogeneous integration, otherwise known as chiplet assembly, brings new kinds of design and manufacturing flexibility to semiconductor and system companies by allowing chips of various technologies, functions and sizes to be integrated in one package.

Die-to-wafer

Die-to-wafer hybrid bonding uses direct, copper-to-copper interconnects to increase I/O density and shorten the wiring length between chiplets to improve overall performance, power and cost. To accelerate development of this technology, Applied is adding the ability to model and simulate this type of bonding to its Advanced Packaging Development Center in Singapore. This builds upon the joint development agreement announced in October 2020 between Applied and BE Semiconductor Industries NV (Duiven, The Netherlands) to develop an equipment solution for die-based hybrid bonding.

Wafer-to-wafer

Wafer-to-wafer bonding enables chipmakers to build certain chip structures on one wafer and others on a second wafer and then bond the wafers to create complete devices. In order to achieve high performance and yield, the quality of the front-end processing steps is critical as is the precise uniformity and alignment of the wafers as they are being bonded.

Applied has reached a joint development agreement with EV Group (EVG) to develop co-optimized solutions for wafer-to-wafer bonding (see EV Group, ASM partner for 3D-IC, chiplet bonding). The collaboration brings together Applied’s semiconductor process expertise in deposition, planarization, implant, metrology and inspection with EVG’s leadership in wafer bonding, wafer pre-treatment and activation, as well as alignment and bond overlay metrology.

Next: Larger substrates


Applied said it will use the panel-level processing technology from its recent acquisition of Tango Systems Inc. (San Jose, Calif.) to offer substrates up to and beyond 500mm by 500mm. Tango is a specialist in sputtering technologies applied to substrates such as PCBs and glass and thin-film electromagnetic shielding applications.

Applied will also provide semiconductor customers with access to large-area materials engineering technologies from its Display Group, including deposition, eBeam testing, SEM review and metrology, and focused ion beam for defect analysis.

Related links and articles:

www.appliedmaterials.com

www.besi.com

www.evgroup.com

News articles:

Capex for advanced packaging to near $7bn in 2021

Samsung improves interposer-based packaging

Intel invests $3.5 billion in chiplet packaging

ARM pushes chiplets and 3D packaging for Neoverse chips

Italian EDA startup offers IC, package co-design tool

EV Group, ASM partner for 3D-IC, chiplet bonding

Intel, Samsung, TSMC to drive chip packaging forward

Chiplet-savvy TSMC to build $10 billion assembly and test plant

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