Arasan Chip Systems develops MIPI compliant Low Latency Interface (LLI) IP solution
Both the Applications Processor and the Baseband Processor for mobile platforms are complex SOCs. Although the two chips are often integrated into one SoC by a number of chip vendors, a number of high end mobile chipsets are still split into two separate processors. They each have their own system level memory to allow efficient cache refills. LLI is a chip-to-chip link layer interconnect protocol that allows efficient , low-latency cache refills from the DRAM associated with a companion chip, thereby removing the need for two separate sets of DRAM’s and substantially reducing the cost of mobile platforms. LLI requires M-PHY Type 1 as the physical layer.
Arasan has developed a combined LLI controller and M-PHY Type 1 solution, which can be configured for a variety of host buses (like AHB, AXI and OCP), and bandwidth/latency requirements across multiple traffic classes. Using up to six lanes of M-PHY’s this solution offers up to 17 Gbps bandwidth in each direction, with only one clock domain crossing in the LLI controller. Customers are given a choice of either source synchronous or independent clocking in the M-PHY’s for clock and data recovery mechanisms in the analog receivers.
"We have invested extensively to co-architect and co-develop the LLI controller and the M-PHY to be rapidly configured and deployed to the myriad of SoC and interconnect architectures in the customer base", said Ajay Jain, Director of Product Marketing at Arasan. "Bandwidth, latency, test compliance, power, area, QoS and compatibility are issues that had to be addressed at a holistic level across the two IP’s before they can be effectively leveraged at the broader system level."
Arasan is ready to engage with customers starting at an architectural consulting level, all the way through the delivery of a properly configured LLI controller RTL and M-PHY macro. As with all other Arasan IP’s, these are delivered with accompanying Verification IP and several other scripts and files required for successful integration into each companion chip.
Availability
Arasan’s MIPI LLI Controller IP Core is available immediately for licensing, including Verilog HDL of the IP Core, Verification IP, synthesis scripts, and documentation. The corresponding M-PHY IP is available as a hard macro targeted to any process node, along with all the customer required support files and documentation.
Arasan plans to hold a webinar on May 16, 2012 to disclose further information on this solution. Attendees can register at arasan.com/webinars
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