ARC-based IP subsystem targets sensor integration

ARC-based IP subsystem targets sensor integration

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By eeNews Europe

The DesignWare Sensor IP Subsystem is optimized for processing data from digital and analogue sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.
The fully configurable subsystem consists of a DesignWare ARC EM4 32-bit processor, digital interfaces, analogue-to-digital data converters (ADCs), hardware accelerators, a comprehensive software library of DSP functions and software I/O drivers. Synopsys acquired UK-based processor designer ARC in 2010 as part of Virage Logic.
Sensors are becoming ubiquitous. Many applications, such as the Internet of Things, automobiles, and mobile devices, increasingly rely on the ability to read and interpret environmental conditions such as pressure, temperature, motion, and proximity. By pre-integrating sensor-specific IP blocks with an efficient processor and software in a single subsystem, Synopsys gives designers an SoC-ready sensor solution that can significantly reduce their design and integration effort, lower design risk and accelerate time-to-market.
“The total number of sensor units is estimated to grow from just under 10 billion in 2012 to nearly 30 billion in 2017,” said Tony Massimini, chief of technology at Semico Research. “As more semiconductor suppliers integrate sensor interfaces into their SoCs, the use of sensor IP subsystems such as Synopsys’ DesignWare Sensor IP Subsystem will significantly reduce their integration effort and cost.”
The DesignWare Sensor IP Subsystem features the power and area efficient DesignWare ARC EM4 32-bit processor core, which includes custom extensions and instructions that support application-specific hardware accelerators and tightly integrated peripherals. The subsystem includes multiple configurable GPIO, SPI and I2C digital interfaces for off-chip sensor connections as well as ARM AMBA AHB and APB protocol system interfaces to ease integration into the full SoC. Over ten configurable hardware accelerators reduce memory footprint and decrease power consumption by a factor of 10 compared to equivalent discrete component implementations and enables implementations as small as 0.01mm2, consuming less than 4uW/MHZ in a 28nm process.
The analog interfaces include low-power high-resolution ADCs that efficiently digitize sensor data for the processor. The sensor subsystem’s HAPS FPGA-based prototyping solution enables immediate software development and provides a scalable platform for rapid full system integration and validation. Synopsys also offers SoC integration services to help customers integrate the subsystem into their chip or customize it to meet their unique application requirements.
“As the technology leader in magnetic sensor ICs for the automotive market, it is critical that Allegro acquires high-quality IP from a trusted provider such as Synopsys,” said Robert Fortin, director of sensors business unit at Allegro Microsystems. “Based on our experience, the DesignWare ARC 32-bit processor’s combination of high performance, small area and low power provides key advantages for sensor design over alternative solutions.”
The DesignWare Sensor IP Subsystem offers a library of DSP functions, including mathematical, complex math, filtering (FIR, IIR, correlation, etc.), matrix/vector and decimation/interpolation that help accelerate sensor application code development. In addition, peripheral software drivers are provided to ease integration of the I/O with the ARC EM4 processor, and host drivers are provided to interface the DesignWare Sensor IP Subsystem to the host processor.
The sensor-specific software functions can also be implemented in hardware to boost performance efficiency and reduce memory footprint. An easy-to-use configuration tool in combination with sensor-specific architectural templates allow designers to quickly select options such as the DSP functions and digital interfaces required for their specific application, enabling a complete sensor subsystem to be configured in hours instead of weeks.
“The industry is seeing significant proliferation of sensor-enabled devices in homes, cars and on-the-go,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “These devices require integrated sensor SoCs that deliver high performance, small area and low power consumption. Synopsys’ pre-verified, SoC-ready sensor subsystem provides designers with a higher level of hardware and software IP integration, enabling them to achieve their design goals faster and with significantly less risk.”
The DesignWare Sensor IP Subsystem is targeted for availability in October 2013 to early adopters, with general availability planned for Q4 2013.

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