Are you bored with your board? How PCB substrates affect aerospace apps
Ka-band, RF carriers, broadband ADCs/DACs, noisy switching regulators, low-voltage high-current FPGAs containing multi-gigabit, high-speed serial links, as well as I/O toggling around 1 GHz, all now reside on the same PCB separated by only a few centimetres. The choice of dielectric now has to optimise for RF, analogue, and digital requirements.
Manufacturers of spacecraft avionics are considering new PCB materials with lower relative dielectric constants (Er or Dk) and dissipation factors (Df) to achieve the performances that will enable future missions for satellite operators. For some designs, careful floor-planning and component placement will allow OEMs to deliver the target requirements using existing, lower-cost materials and less expensive fabrication.
At lower frequencies and data rates, signal loss is caused mainly by impedance mismatches: and less so, by dielectric absorption and conductor losses. At higher frequencies, material loss becomes equally important and controlled substrate construction must be considered during the design process.
At higher frequencies (and faster edges), losses occur due to changes in characteristic impedance (Z0), absorption of some of the signal energy by the dielectric material, and resistive channel losses due to skin effect and copper-surface roughness. Reflections are caused by impedance discontinuities, variations in Z0 resulting from differences in laminate thickness, changes in the dielectric constant of the substrate, and fabrication tolerances in the width of the etched traces.
The dielectric constant (Er/Dk) of nearly all PCB substrates decreases with frequency, which manifests itself in two ways: the speed of signals increases and the characteristic impedance of a transmission line becomes smaller. The former generates phase distortion in bandwidth-rich digital signals, while changes in Z0 cause faster edges to reflect more than slower ones. Edges contain harmonics which can have significant amplitudes up to a frequency of 0.35/T, where T is the smaller of rise or fall time in ns.
Within the dielectric, the fibreglass weave pattern and the ratio of reinforcement to resin cause local variations in Er/Dk. The glass and epoxy each have different relative permittivities, thereby presenting a non-homogenous medium for signal propagation.
The tighter the weave netting, the more uniform the dielectric constant. Loose weaves result in more variation within the laminate, causing variations in trace impedance and propagation skews in tightly matched signals, such as differential pairs, which directly reference the weave. Some patterns are shown below.
Figure 1 Different styles of fibreglass weaves impact the dielectric constant, trace impedance, and propagation skews.
For example, on a sparse weaving… (continues)
For example, on a sparse weaving such as glass style 106, one leg of the differential pair may be routed directly over a fibre while the other leg is routed between the weaves, as illustrated in Figure 2. This results in a different Er/Dk for each leg of the differential channel, which introduces skew between the two traces and, depending on the data rate, can impact the unit interval (UI) affecting the quality of the eye seen at the receiver.
Figure 2 On a sparse weaving, one leg of the differential pair may be routed directly over a fibre while the other leg is routed between the weaves. Image courtesy of Isola.
When components are flow-soldered onto a PCB and the board is subjected to temperature cycling, or for missions that require the avionics to operate at elevated temperatures, the designer must be aware of the Glass-Transition Temperature (Tg). This is when the resin in the material begins to expand much faster than the expansion of the surrounding glass weave and copper, with the potential to cause volume growth in the Z direction. The resulting stresses can fracture vias and lead to delamination, in extreme cases. A material’s Coefficient of Thermal Expansion (CTE) behaviour can change drastically above Tg, becoming mechanically and electrically unstable.
Temperature can also affect… (continues)
Temperature can also affect the electrical performance of a PCB as Er varies as a function of temperature, defined by a parameter known as the Thermal Coefficient of Dielectric Constant. Z0 is determined not only by the thickness of the substrate material but also by Dk, and changes in z-axis CTE and Er due to temperature can significantly impact the impedance of transmission lines fabricated on that material.
The latest flip-chip packages have low CTE compared to traditional, space-grade PCB materials, and this mismatch is presenting some manufacturing challenges for OEMs. Low-power, high current FPGAs require careful thermal management and heavier copper or the use of copper invar copper, copper molybdenum copper, aluminium and carbon composites to balance thermal conductivity and CTE. A PCB material’s thermal conductivity can be used as a relative indicator of a laminate’s effectiveness in dissipating heat.
Isola’s Tachyon 100G and I-Tera MT materials offer potential for future space applications, and Rogers Corporation also has some interesting prepregs. Isola specifically developed its GigaSync and Chronon laminates to address high-speed PCB design issues. The following table compares some dielectrics currently being used or considered by the space industry.
For cost-conscious sub-systems, careful floor-planning and layout techniques can avoid the need for more expensive materials and PCB fabrication. Placing components close together minimises trace lengths and dissipation loss, while zig-zag or jogged routing can mitigate the effects of fibre weave as traces are routed on and off weave repeatedly as shown below.
Figure 3 Zig-zag and jogged routing can mitigate the effects of fibre weave.
For cost-sensitive sub-systems wanting to exploit the benefits of high-speed serial links, the use of pre-emphasis and equalisation will compensate for some of the channel loss. For some applications, this will allow PCB fabrication using traditional, less-expensive FR4 substrates or mid-performance materials.
To deliver future satellite sub-systems cost-effectively, designers must understand the material properties that influence signal loss, signal integrity, and PCB manufacturability to deliver the required mission performance within budget.
About the Author
Dr. Rajan Bedi is currently CEO of design consultancy Spacechips (Hertfordshire, UK). Rajan worked at Astrium (now Airbus) for twelve years developing and researching space-grade electronics for telecommunication, navigation, Earth-observation and science missions. As Head of the Mixed-Signal Design Group, Rajan’s team developed the hardware for the award-winning, channelising payload currently operating on-board the Alphasat telecommunication satellite.
Rajan adds; “I have created a new LinkedIn group called Out-of-this-World FPGAs to discuss space-grade FPGAs. I hope this will become a forum used by semiconductor suppliers to gauge feedback from the space-electronics community, design engineers working for satellite and launch OEMs, as well as operators, to openly talk about technical and commercial aspects of space-grade FPGAs. So if you are interested in improving your knowledge of RTAX, RTG, V5QV, Eclipse, ATF, COTS FPGAs for space, Libero SoC, IDE, Vivado, ISE, Figaro and so on, then join the fun – it’s independent and down-to-Earth!”
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