ARM bids for chiplet dominance
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ARM has launched two programmes to boost its position in chiplet designs around cores and interconnect.
ARM cites the need for a common framework that requires significant and focused collaboration with the ARM Chiplet System Architecture (CSA) and a new version of the CHI interconnect.
The chiplet system architecture brings together 20 partners to analyze and define the optimal partitioning choices for chiplet-based systems. The goal is to develop the CSA to allow greater reuse of components between multiple suppliers. The partners range from mobile to automotive to infrastructure including how to partition an ARM-based system across multiple chiplets, or the high-level properties such as requirements for system memory or a Root of Trust.
AMBA CHI is high speed, credited, and packetized, which makes it ideal for chiplets. The AMBA CHI C2C specification, developed with Nvidia, uses the existing on-chip CHI protocol and defines how it is packetized, enabling it to be transported from chiplet-to-chiple). The specification has now been released after collaboration with a diverse set of partners.
“Our investments into AMBA and CSA will enable partners to decompose an ARM-based system across multiple chiplets, in the same way a monolithic chip is composed of IP blocks. Alongside these new standards, there are several ARM-specific and industry-wide layers we need to continue to collaborate on,” said Richard Gristlenthwaite, EVP, Chief Architect & Fellow at ARM.
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The AMBA CHI C2C specification takes the existing single chip CHI protocol and defines how it is packetized, which enables it to be transported chiplet-to-chiplet. As AMBA already connects the different components in a single chip, the natural progression through the CHI C2C specification is extending this connectivity across multiple chiplets.
This uses many features from the existing on-chip AMBA CHI specification. CHI C2C inherits the existing on-chip protocol to avoid incompatibilities. It allows the same architecture features from the existing AMBA specifications to be used across chiplets, like realm management for confidential compute. There is also no complex packing or unpacking with CHI C2C, which minimizes latency. As with AMBA for existing on-chip designs, ARM expects CHI C2C to be used across very high-performance systems that have a vast number of processors and components including custom silicon. With different chiplet components coming from various vendors, CHI C2C ensures maximum interoperability for chiplets through a single, unified interface. These include chiplet designs for AI acceleration.
As CHI C2C follows a layered approach that offers a clean separation of layers, it can use third-party and industry standards, like the Universal Chiplet Interconnect Express (UCIe) standard. UCIe is particularly important to CHI C2C, as it helps to standardize die-to-die connectivity in multi-die systems and also streamlines interoperability between dies on different process technologies from different suppliers. In fact, CHI C2C is completely complementary to UCIe, as it can be transported over UCIe through its streaming interface.
As well as Nvidia, the partners in the AMBA CHI C2C specification include Arteris, Cadence, Fujitsu, Intel Foundry Services, Rambus, Sanechips, Siemens EDA, SiPearl and Synopsys.
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“The release of the first public CHI C2C specification marks a significant step towards an open chiplet ecosystem and contributes to improvements in interoperability. We are pleased to partner with Arm on early AMBA developments as it will impact future versions of our high-bandwidth, low-latency network-on-chip interconnect IP technology including Ncore and FlexNoC. We look forward to further cooperation across the emerging chiplet ecosystem,” said Laurent Moll, COO of Arteris.
“With its disaggregated solutions in the form of chiplets, droplets, dielets, tiles and such, the More-than-Moore era presents significant opportunities and technology challenges for both designers and implementers. The need for standardized interfaces is paramount to facilitate communication between chiplets from a multitude of providers and to avoid building a tower of Babel. Cadence has a history of close collaboration with Arm on AMBA standards, and we’re pleased to build upon our partnership and bring the new AMBA CHI C2C standard to market in our IP and chiplet solutions encompassing flows, reference designs and customer designs. This important new standard will be a key ecosystem enabler and should promote an open chiplet marketplace, which is still in its nascent stage,” said David Glasco, VP of R&D for the Silicon Solutions Group at Cadence
“Intel has long envisioned a “chiplet revolution,” which was the motivation for our introducing the UCIe protocol to the industry in 2022. We are pleased to see the industry’s growth and adoption of UCIe™, advanced packaging technologies, and standards-based protocol mapping. Along with UCIe, the standardization and release of the AMBA CHI C2C specification is a critical building block for the industry’s drive toward chiplet based architectures,” said Bob Brennan, IFS, VP, Customer Solutions Engineering at Intel which intends to show the first heterogeneous chiplet implementation.
“Siemens EDA is pleased to support the development of AMBA, taking AMBA CHI C2C protocol to the growing chiplet ecosystem, which is an area of Siemens’ focus with our Avery Verification IP and Veloce hardware-assisted verification solutions,” said Abhi Kolpekwar, VP and General Manager of Digital Verification Technology at Siemens EDA.
The CHI C2C specification follows the existing AMBA licensing model. This means it is freely available, royalty free, architecture neutral, and has broad and perpetual implementation rights.
“While mass market adoption of chiplets is likely to take many years to reach mass-market adoption, we’re excited by the potential these standards have to expedite the journey towards chiplet-based systems,2 said Gristenthwaite. “The flexibility of the ARM platform is enabling the emerging chiplet ecosystem today – it’s a natural progression in our heritage of enabling partners to build custom silicon solutions quickly with the flexibility they need.”
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