ARM launches highest performance Cortex M85 core in voice recognition subsystem

ARM launches highest performance Cortex M85 core in voice recognition subsystem

Business news |
By Nick Flaherty

ARM has launched its highest performance microcontroller core, the Cortex M85, with security enhancements and a pre-validated sub-system for voice recognition systems.

The M85 provides up to 6 CoreMark instructions per MHz and is integrated into the pre-validated Corston 310 voice recognition subsystem. The M85 adds the Helium vector processing engine for machine learning, and the 310 allows for an optional Ethos U55 AI accelerator core.

“We have added microarchitecture for more scalar performance and added the Helium vector engine for machine learning,” said Mohammed Awad, vice president of IoT and embedded at ARM told eeNews Europe. “Any workload that can be vectorised would benefit from Helium, typically DSP and ML workloads.”

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The M85 is using dual instruction issue with selective triple issue with intelligent control for the branch prediction. This boosts the performance by 30% over the M7 core and 85% over the M55.

This will also be used for a Corstone sub-system codenamed Kochab for image processing with an optimised neural processing unit accelerator.

The M85 also uses the Pointer Authentication (PAC) and Branch Target Identification extensions from the ARM v8.1-M architecture to protect against intrusions and malware as well as secure enclave for storing data.

“Security is key for the Internet of Things (IoT) so the M85 is the first Cortex with PAC from v8.1 for added protection against malware – this significantly accelerates development time,” said Awad. “The secure enclave means a device is immediately ready for PSA certification to accelerate time to market.”

At the same time ARM has released virtual models of all its M-class controller cores, as well as virtual models for popular chips.

“We are also supporting ARM virtual hardware support for third parties with ST, NXP and a virtual Pi 4B who provided the data we needed but we are opening this up to other silicon partners and OEMs,” he said.

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