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ARM describes 10nm test chip

ARM describes 10nm test chip

Technology News |
By Julien Happich



The ARM test chip used four of its yet-to-be-disclosed Artemis cores running at 2.8 GHz, an unknown GPU and memory subsystem among other components. Unlike previous nodes, the TSMC 10nm process is focused less on pushing performance to the max and more on lowering power consumption, ARM said.

Test chip architecture Source: ARM

Compared with a Cortex A-72 on TSMC’s 16FF+ process, the 10nm SoC operating on the same frequency showed a 0.7%, 11% and 12% improvement in performance depending on the use of overdrive which ARM defines as nominal + 100 mV. Eventually, 10nm chips should show a 30% improvement in power consumption compared with its predecessors.

The Artemis core itself appears to be focused mainly on lowering power consumption and size based on ARM’s comments about the test chip.

Data on total power versus performance of 10nm FinFET test chips compared to 16nm FinFET. Source: ARM

“Artemis is a small core, so you’re going to get some architectural benefits in leakage, just as much frequency, better power and smaller,” said Ron Moore, vice president of marketing for ARM’s physical design group. “Performance between Artemis and an A-72 are going to be pretty much at the same level.”

TSMC has been working closely with ARM on process technology and IP for the past four years. However, ARM also is working with Samsung as its foundry aggressively pushes toward its own 10nm FinFET process.

While Samsung and TSMC race to be the first to market with a 10nm node, Moore isn’t concerned about who comes in first. “The fin size is different but I can accomplish the same thing using Artemis in both processes,” he told EE Times.


Jim McGregor, Tirias Research principal analyst, expects Samsung and TSMC to continue to battle it out but also run into some of the same challenges Intel faced when ramping 14nm.

“Both these guys are ramping aggressively with ARM-based products. That really shows the strength of the ARM architecture,” McGregor told EE Times. “If you had to compare process to process, when Intel gets to 10nm they’ll probably still have the most aggressive process of any of them, but Intel hasn’t shown their ability to be an effective foundry,” he said.

Moving to the 10nm node comes with additional costs. Moore said the design cost for developing a physical implementation of 28nm was about $5.5 million, while 10nm will cost approximately $32.5 million – a figure initially given by International Business Strategies in August 2015. A 10nm chip requires more iterations, IP, and likely more machine time – all of which is likely to trickle down as additional costs for chip designers and their foundries, he said.

“The early ones in pay for the early development cost. They pay for the high really expensive design tools, they pay the big premiums because they can afford more and because their markets are bigger,” said VLSI Research CEO G. Dan Hutcheson. “I think the cost-to-design argument, to some extent, is a bragging right.”

Hutcheson continued that the general design cost for a chip shouldn’t be more than 15% of its sale price, and added that there is a lot of complexity in that design figure. The amount of IP in the ecosystem, the cost of a design team, the capability of design tools and the size of the market all play into that $32 million figure – which will shrink as 10nm proliferates.

At an analyst event, ARM didn’t provide updates on a lower-cost alternative, fully-depleted silicon on insulator (FD-SOI), which the company acknowledged as a viable technology during the FD-SOI Symposium last month.


“FD-SOI is still very much a good technology and it is a very power efficient technology,” Moore said.

“We do not see the customer adoption and the ecosystem. What you’re missing is the LPDDRs, the memory interfaces, the IP kind of stuff,” he said. “FD-SOI is probably not being adopted as well as it could because the ecosystem is trailing. I think the foundries that want to do the FD-SOI will have to invest,” he added.

One of the challenges of FD-SOI adoption is the analog, RF and high speed interface IP needed to support diverse market segments, Moore told EE Times, pointing to the needs in mobile, enterprise, and embedded/IoT markets.

ARM already ports devices to FD-SOI, Hutchenson noted, though the porting process is tedious. The issue isn’t the ARM core but supporting a variety of ecosystems and thousands of potential IP. Moore said foundries will need to provide “seed funding” to build out the IP ecosystem for each of market, including porting complex IP from BULK to FD-SOI.

Kelvin Low, Samsung’s senior director of foundry marketing, said his company has “substantial IPs” for FD-SOI that have been product tested. A GlobalFoundries’ representative said the company will support FD-SOI for SoCs by the second half of 2017.

“We are developing IP [on our 22FDX platform] concurrently with technology development,” a GlobalFoundries spokesman said.

“Some of them have gone through early silicon validation and others are in various stages of design and silicon validation,” he said. “Prototype SoCs are being taped out now using early versions of IPs. A complete set of silicon validated foundation and complex IPs will be available for SoC design start and tapeout, [and] we are on target to support SoC product launch in 2H2017,” he added.

“No company has the breadth of the entire ecosystem of IP,” Hutcheson told EE Times. “If I were to guess, it’s in their advantage to minimize the number of ecosystems they have to support.”

 

About the author:

Jessica Lipsky is Associate Editor at EE Times

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