ARM readies computing ecosystem for autonomous driving
Designers of embedded application know it: The world’s most common processor architecture is not Intel’s X86, but Arm’s architecture. Arm IP is also used in cars – in SoCs, as a component of ASICs and in a variety of chips for special embedded applications. Arm processors are used in 65 percent of ADAS systems, says Lakshmi Mandyam, Vice President Automotive at Arm. However, for use in autonomous driving according to SAE levels 4 and 5 (“eyes off” and “mind off”), new computer architectures with new features are needed. Today’s prototypes of autonomous cars drive around with a trunk full of computers, which of course won’t work in series production. Arm’s Mandyam estimates that a multiple of today’s number crunching capacity power is required for this, but at the same time such systems in series production are only allowed to consume a tenth of the electrical power. Likewise, the costs for these systems must be reduced by a factor of 10. This is still not enough – the systems must also comply with the ISO26262 standard for functional safety.
Therefore, Arm has launched an extensive development program to satisfy all these requirements. In future, the company’s IP partners will not only be able to license the corresponding processor IP, but also certified software components and development tools. Arm will also provide the documentation required for certification according to ISO26262.
A cornerstone of Arm’s product strategy for autonomous driving is the Cortex-A76AE processor. The AE in the processor name stands for Automotive Enhanced. With its split-lock technology, this architecture is specially designed to meet the requirements of safety-relevant applications. Split-lock means: For safety-critical applications, two parallel processor cores can be coupled together using the lockstep method. This is a common procedure for safety-critical applications in which the identical software runs on both cores; the cores monitor each other. For applications where high computing power is more important, the cores can also be connected in parallel and their performance increased accordingly.
This feature gives developers the flexibility they are missing in previous lockstep implementations, Arm’s Mandyam advertises. CPU clusters in an a SoC can be configured either in ‘split mode’ for high performance, where two (or four) independent CPUs in the cluster that can be used for diverse tasks and applications, or in ‘lock mode’ where CPUs are in lockstep, creating one (or two) pairs of locked CPUs in a cluster, for higher safety integrity applications. In addition, the CPU clusters can be configured to operate in a mix of either mode, post Silicon production.
Arm’s Automotive Enhanced ecosystem includes system IP for designing comprehensive autonomous-class SoCs. Critical elements include a new CoreLink GIC-600AE, CoreLink MMU-600AE and CoreLink CMN-600AE, provide features such as high-performance interrupt management, extended virtualization and memory management, and connectivity to multiple CPU clusters to scale performance in safe multicore systems. These products have been designed to enable high-performance systems, targeting ASIL-B to ASIL-D safety integrity, and support the Split-Lock and systematic capabilities for functional safety designed into the Cortex-A76AE.
These products and features will be rolled out over the next couple of years, Arm explained. The Cortex-A76AE is already optimized for 7nm semiconductor processes. Over time, the AE processor IP will be accompanied by additional architectures in various constellations.
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