ARM shows Cortex-X4 core, DSU for laptop chips
ARM has launched its latest ‘Total Compute Solution’ (TCS) with its fastest ever processor core, the X4 and a core management system for chips on TSMC’s 3nm process and Intel’s 18A process.
This may go some way to addressing the confusion over ARM reported to be making a chip, as TCS includes all the elements and sub-systems that would be needed to produce a chip. The IP needs to be proven in silicon, and delivering a prototype ‘chip’ is a key part of the development process. This is especially important as the latest version, TCS23, is aimed at chips produced TSMC’s N3E 3nm process and Intel’s 18A.
The roll out is supported by EDA tools from Synopsys and Cadence Design Systems. ARM used the Cadence Cerebrus AI-enabled tool for the design of an implementation of the Cortex-X4.
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As well as the X4 core with a 15% increase in performance over the X3, TCS23 includes an updated DynamIQ Shared Unit, or DSU, which is arguable more important. The DSU120 supports up to 14 cores in a sub-system with power and performance management and up to 32Mbits of L3 cache.
The DSU can manage ten X4 cores with four A720s for laptop chips, as well as an eight core CPU cluster with one Cortex-X4, five Cortex-A720 and two Cortex-A520 for more IoT edge AI chips. Laptop chips are a key area of discussion ith leading licensee Qualcomm which is developing its own.
The DSU also allows an X4 core with high performance alongside four A520 cores, also new, and four A720 cores for a more sophisticated big.LITTLE architecture in flagship smartphones. Mediatek in Taiwan is the lead chip developer for the core, and was also one of the first to sign up for Intel’s Foundry Service.
“ARM’s innovative 2023 IP, the Cortex-X4 and Cortex-A720, and Immortalis G720 have provided an excellent foundation for our next-generation Dimensity flagship 5G smartphone chip.” said Dr. JC Hsu, Corporate Senior Vice President and General Manager of Wireless Communications Business Unit, MediaTek
“The combination of leading-edge Intel 18A technology with ARM’s newest and most powerful CPU core, the Cortex-X4, will create opportunities for companies looking to design the next generation of innovative mobile SoCs. ARM is a critical partner as we work to build a comprehensive foundry ecosystem for our customers around the world,” said Stuart Pann, Senior Vice President and General Manager, Intel Foundry Services (IFS).
These are all built on the Armv9.2 architecture, which alongside Memory Tagging Extension (MTE) for 64bit Android operating system security and SVE2 for more software performance, adds a new QARMA3 algorithm for Pointer Authentication (PAC) to remove memory bottlenecks with security.
This works with Pointer Authentication (PAC) and Branch Target Identification (BTI) to improve control flow integrity by eliminating almost all Jump-Oriented Programming (JOP) and Return-Oriented Programming (ROP) vulnerabilities with negligible performance hit for the X4 and A720 CPU cores. The PAC enhancements, including the new QARMA3 algorithm, reduce the performance impact of PAC and BTI to less than one percent for A520 CPU cores.
“TCS23 delivers a complete package of the latest IP designed and optimized for specific workloads to work seamlessly together as a complete system,” said Chris Bergey, senior vice president and general manager, Client Line of Business at ARM.
TCS23 also includes a new Immortalis-G720 GPU based on ARM’s fifth Generation GPU architecture. This uses Deferred Vertex Shading (DVS), a new graphics feature, to scale for larger core counts and higher performance points.
Synopsys EDA tools
TCS23 is supported by AI-enabled tools from Synopsys. These include the Synopsys.ai full-stack AI-driven EDA suite, which taps into the power of AI from system architecture through manufacturing to optimize power, performance and area (PPA) and enhance time to market.
The Synopsys Verification family includes support for the Cortex-X4, Cortex-A720 and Cortex-A520 CPUs and Immortalis-G720 and Mali-G720 GPUs. Early adopters of TCS23 are using Synopsys virtual prototypes with ARM Fast Models, Synopsys hardware-assisted verification and verification IP for the latest AMBA interconnect.
Synopsys also has Interface and Security IP for PCI Express 6.0 with Integrity and Data Encryption (IDE), CXL 3.0 with IDE, DDR5 with Inline Memory Encryption (IME) and UCIe, all of which are optimized for performance with ARM-specific features and for pre-silicon interoperability with ARM cores.
Synopsys Silicon Lifecycle Management Family PVT monitor IP, developed in the UK, can also be integrated into ARM cores to monitor chip health from development to the field to measure and optimize performance.
Synopsys Fusion QuickStart Implementation Kits (QIKs) are tuned to extract maximum entitlement from the latest 5, 4 and 3nm process technologies. These include implementation scripts and reference guides that enable early adopters of the newest Armv9.2 cores to accelerate time to market and achieve their demanding performance-per-Watt targets. These QIKs are available today on request.
Cadence EDA tools
Cadence fine-tuned its RTL-to-GDS digital flow and delivered corresponding 3nm and 5nm Rapid Adoption Kits (RAKs) for the Cortex-X4, Cortex-A720 and Cortex-A520 CPUs and Immortalis-G720, Mali-G720 and Mali-G620 GPUs as well as optimising the verification flow.
Cadence says using the Cerebrus tool and verification flow gave ARM 50% better timing (TNS), a 10% reduction in cell area and 27% improved leakage power on the Cortex-X4 CPU.
The tools optimized for TCS23 include the Cerebrus Intelligent Chip Explorer, Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking and Conformal Low Power.
Cerebrus automates and scales digital chip design, providing customers with improved productivity versus a manual, iterative approach. iSpatial technology provides an integrated implementation flow, offering improved predictability and PPA, which leads to faster design closure.
The RAKs also incorporate an innovative smart hierarchy flow that enables accelerated turnaround times on large, high-performance CPUs. The Tempus ECO Option, which provides path-based analysis, is integrated into the flow for signoff-accurate, final design closure. The RAKs also use the GigaOpt activity-aware power optimization engine, which is incorporated with the Innovus Implementation System and the Genus Synthesis Solution to dramatically reduce dynamic power consumption.
Arm used the Cadence verification flow to validate the Cortex-X4, Cortex-A720 and Cortex-A520 CPU-based and Immortalis-G720, Mali-G720 and Mali-G620 GPU-based mobile reference platforms. This uses Xcelium Logic Simulation Platform, Palladium Z1 and Z2 Enterprise Emulation Platforms, Helium Virtual and Hybrid Studio, Jasper Formal Verification Platform and Verisium Manager Planning and Coverage Closure tools.
Cadence also validated that Cadence Perspec System Verifier, VIP and System VIP tools all support TCS23-based designs to enable customers to accelerate time to market when assembling TCS23-based SoCs. This includes ARM Fast Models to enable early software development and verification through the Cadence Helium Studio as well as the Cadence Palladium and Protium platforms.
“With the delivery of Arm TCS23, we’re unlocking the creative potential for customers around the world who demand high performance and efficient compute for next-generation mobile experiences,” said Bergey. “Through our ongoing collaboration with Cadence, we successfully leveraged the Cadence digital and verification flows to get our latest generation of CPUs and GPUs into our customer’s hands faster and accelerate time to market.”
www.arm.com; www.synopsys.com; www.cadence.com/go/armsoltcs23
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