ARM upgrades interconnect, memory control IP

ARM upgrades interconnect, memory control IP

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By eeNews Europe

The Corelink CCI-550 provides 1 to 6 ACE interfaces and 1 to 6 memory interfaces, as compared with the maximum four of each provided by the CCI-500. The Corelink supports "big-little" processing and connection to a fully coherent GPU while increasing peak throughput.


The Corelink CCI-550 provide up to a 60 percent bandwidth increase as well as enhancements that reduce latency. An integrated and improved snoop filter function can save hundreds of milliwatts of power consumption, ARM claims.

SoC designers can configure the number of memory channels, tracker sizes, snoop filter capacity and scale up to 6 coherent processor clusters. The technology is suitable for a range of applications 4K resolution imaging in mobile and digital TV as well as automotive and networking applications.

CoreLink DMC-500 – upgraded from DMC-400 – provides support for LPDDR4/3 memory with enhanced quality-of-service for memories operating up to LPDDR4-4267 transfer speeds. When integrated at the design level, CoreLink CCI-550 and CoreLink DMC-500 work together to deliver a peak system memory bandwidth beyond 50GB/s for access to richer content such as 4K video for application in tablets and smartphones.

Both CoreLink products have been delivered to lead partners and are available for licensing with production silicon expected by late 2016, ARM said in a statement.

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