ARM is paying attention to this because of the potential to be highly disruptive in the logic space and therefore at the platform (hardware-software) level, Yeric said. “There’s resistive RAMs of various types and magnetic RAM and TSMC has recently made an embedded ReRAM so there’s a lot going on. ARM has its own DARPA-funded research into correlated electron RAM (CeRAM, see Applied, ARM to develop CeRAM for neuromorphic applications).”
Yeric explained that at 28nm flash memory cannot really scale any more – hence the move to 3D stacking for stand-alone flash memories. “Flash is power hungry and very slow.”
To try and exploit this opportunity several memory technologies have been research and developed over decades, many trying to be the “universal” memory that could replace everything including basic SRAM cells inside logic, but without success so far, said Yeric. There have been numerous partial successes in terms of one performance metric or another. The result has been multiple technologies each targeting different niches and a certain fragmentation and lack of commercial traction, but plenty of grist for the semiconductor research mill, Yeric explained.
So many memories
“Generally ReRAMs don’t have the endurance. MRAM does have the endurance but the on/off ratio is very low,” said Yeric. This means that engineers have had to choose their application targets with care, whether these are solid-state drives – in competition with 3D-NAND flash – or as embedded memory next to microcontrollers, where phase-change memory, ReRAM and MRAM are all contenders.
“There’s a lot of hope that a follow-on version of MRAM could replace SRAM for cache requirements. The IMEC research institute has a project to replace six-transistor SRAM with one-transistor MRAM,” said Yeric. “For microcontroller on-chip memory applications MRAM is the leader,” he agreed.
Next: Game changer
There is the prospect that spin-orbit torque MRAM might get up to the correct speed-endurance trade-off to get inside core logic, said Yeric (see IMEC makes spin-orbit torque MRAM on 300mm silicon). This would allow the advent of something called “normally-off” computing. “It’s a great change,” said Yeric.
The ability to freeze computing processes on-chip, retain state while drawing no power and then resume, would have considerable consequences, Yeric said. “It would require a new processor architecture. I think we would be adding a new processor line; something that could address a different power envelope in the IoT space; working without batteries by using harvested energy. It would also be able to leverage the massive momentum in IoT,” said Yeric.
But these things are not quite a done deal yet. Bringing different materials into the fab always requires care and can ramp adoption costs. This is one reason why there are also non-volatile memories based on more familiar materials such as ferroelectric memory based on hafnium oxide (see Dresden NVM startup raises funds), and ReRAM based on silicon-oxide (see Weebit silicon-oxide ReRAM headed to 28nm, AI). Both materials are used in fabs as insulators but researchers are discovering properties that can be used as memories and making good progress.
And what about the CeRAM being pioneered by Carlos Paz de Araujo, a professor at the University of Colorado, through his company Symetrix Corp. (Colorado Springs, Colo.). ARM has been working with Symetrix since about 2014. Yeric reckons the technology is still two or three years away from commercialization. “It has a chance on paper. It has the endurance, speed and energy but then a lot of non-volatile memories appeared to have a chance at this stage in their development.”
Yeric made the point that the devil is always in the detail of progressing down in process node and up in integration, from bits to arrays to subsystems. “We hope to have something to report at the next ARM Research Summit,” he added.
At this point we changed gear to discuss neuromorphic computing. ARM already has two machine learning processors that are on their way to customers (see ARM launches two machine learning processors). The ARM ML and ARM OD (object detection) were due to be available for licensing mid-2018. But we asked whether analog was ultimately the way to go?
“There are papers out there that suggest analog machine learning is going to be lower power but there are also lots of things to overcome; such as verification of circuits and variability and repeatability in the field,” Yeric said. He also pointed out that something may offer a tremendous uplift in the depths of the compute kernel but that advantage can become “washed out” at the system level. This can make a significant change less than worthwhile.
A second factor is memory management and interface to other digital circuitry can become complex.
“The third issue is EDA. The EDA industry doesn’t tend to speculate and that provides a chicken and egg problem. That’s true in non-volatile memory, cryogenics and 3D design. So part of the research path is building miniature ecosystems to support potential technical directions.”
Next: Not the same
But Yeric added that with future nodes the broader market may have to get over the idea that all chips are identical, behave the same, and produced using a cookie cutter manufacturing approach.
The complexity of modern electronic systems has already produced a degree of non-determinism at the system level, Yeric obeserved. With unsupervised learning and chips that adapt to the inputs they are exposed to, that non-determinism will be at the root of electronics, but it may also be necessary to achieve manufacturing yields and energy efficient computation.
While Yeric is not committing to analog neuromorphics, the evidence is there that biological computers – such as the human brain – offer far higher energy efficiency than artificial systems and are analog.
Roll with plastic
We then moved on to plastic electronics but this is something that could be further out. “Maybe 10 or 15 years at least in terms of microcontroller implementations,” said Yeric. But there are strong reasons to study it, mainly cost, he said. There is high minimum cost and entry point for building a fab and that produces relatively high per chip costs.
The problems are a lack of transistor performance and a lack of good complementary transistors – lack of good p-type transistor – to allow CMOS design in plastic. This limits potential applications, for now, said Yeric.
“But roll-to-roll production could get chips that start at the sub one cent level and would provide a break from the lithography paradigm. This in turn would allow lots of different versions of the same chip to be made and tried in the market,” said Yeric. This is the way software and software services are introduced allowing customer feedback to dictate the long-lasting features. “It would allow a sort of genetic evolution in manufacturing.”
“At 7nm CMOS you can only afford to design one circuit and it better be right. Plastic circuit production would allow a different paradigm. To make multiple circuits and see which ones behave best.”
There is also potential to make circuits dissolvable and therefore recyclable, improving the sustainability of electronics, although also limits performance metrics achievable. “From an ARM core perspective it may be further away but in some areas it is close. RFID for example where it is already used for asset tracking. Flexible displays is another great area. A third is neural networks (see ARM’s next bet for plastic chips: neural networks).
Next: CFET stacks up
We also took the opportunity to ask Yeric about the industry’s silicon manufacturing roadmap and ARM’s view of the likely path beyond 3nm where there is considerable uncertainty.
Yeric: “We’re going to need new ways of doing things to get to 2nm and 1nm. We do have a physical IP business and we need to pay attention because they may need to make changes at some point.”
Yeric said that right now the emerging favourite is to go to multiple channels in a FinFET in the so called “nanosheet” approach and then to stack p- and n-type FinFETs one above the other in the so-called complementary FET or CFET configuration (see IMEC presents ‘n-over-p’ complementary FET proposal). And after that is possible to think of applying 3D stacking learning from 3D-NAND to logic. “At a cost level that is an alternative but we don’t know about power and performance. But we are already getting used to not seeing those power-performance benefits,” said Yeric.
A lack of performance uplift and power saving from miniaturization means that value has to be created in design and if anything that plays to ARM’s strength, he said. “With ideas like memory near compute, compute in memory and so on, there is plenty of opportunity a the system level,” he said.
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