ARM is best known for its now lengthy roadmap of CPU processors made available as licensable cores. But it has also moved out into graphics processors, on-chip busses, wireless IP with machine learning cores set to follow soon. Is that process on-going in wireless and 5G?
In the embedded sector ARM has the Cordio range of Bluetooth and 802.15.4 supporting wireless IP covering both hardware and software and that has been added to with the Cordio-N hardware and software for Narrow-band IoT (see ARM buys startups for NB-IoT expertise). “But 2G/3G modems? It’s not interesting to do that. The cellular modem market is established with established player and competitive. But NB-IoT is new and fits in with ARM’s emphasis on security,” said Ronco.
“That said, we are keen to produce CPUs that can be part of a modem. The Cortex-R8 is widely used in 4G modems. But we are not inclined to provide a modem software stack. We work out where we provide the most value,” he added.
It is also the case that 2G is being shut down in some countries and the frequencies re-used and this is where NB-IoT starts to play, added Thomas Ensergueix, senior director for embedded and automotive.
Ronco added that just prior to the Embedded World show and Mobile World Congress ARM had announced an approach to an integrated subscriber identity module (iSIM) and operating system to support it.
SIM cards are best known as the physically manifested and secure identity at the heart of everyone’s mobile phone. ARM is proposing the use of integrated iSIMs as a means to secure the identities of billions of IoT nodes. This will allow the integration of a microcontroller core, cellular modem and SIM identity into a single IoT SoC to reduce device costs.
The ARM Kigen OS provides a GSMA compliant software stack to to enable full integration of SIM functionality into IoT SoC designs an integration with mobile network operator and IoT platforms.
Next: Reduced resolution data types
Ronco on data types
ARM has long argued against the use of 8bit microcontrollers and that the world is turning to 32bit microcontrollers based on its Cortex-M cores. But with the emergence of the IoT and the idea that millions if not billions of nodes must be abstemious in power consumption, the idea of using reduced resolution data types has found renewed traction.
Ronco points out that most ARM cores up to and including the Cortex A75 and Cortex-A55 support 8bit datatypes but that supporting the datatype doesn’t mean you need an 8bit processor.
“These 32bit microprocessors are really low power in any case and the users are writing in C. Compilers can pack the 32bit processor words with four sets of 8 bits so you are using multipliers and registers efficiently. You can also use 32bit processor extensions such as SIMD (single instruction multiple data) for more parallelization. This can even provide benefits over 8bit processors in that the processing can be done faster so the node can return to a standby or sleep mode the quicker and save power by being off for more of the time,” said Ronco.
“Now it is clear that security is the big concern for IoT microcontrollers. And that means it is important that firmware can be updated over the air.”
“Well that was more about out-of-order processing and speculative execution found in high-end processors,” he responded.
Ronco continued: “You will have bugs in code and you need to be able to patch quickly and securely and that means providing security over the whole product life cycle. In the past there has been too much fit and forget.”
In the case of Meltdown and Spectre, Ronco said, the industry took responsibility and smartphones were updated. But M&S only affected higher end processors; Cortex-M, Cortex-R and some Cortex-A, such as Cortex-A53 and Cortex-A55, were not affected, said Ronco.
Ronco on RISC-V
Ronco started with a straight denial that RISC-V would “eat ARM’s lunch” as the saying goes.
RISC-V is an open instruction set architecture (ISA) developed at the University of California Berkley that is based on established reduced instruction set computing (RISC) principles. It is now in the public domain and looked after by the RISC-V Foundation.
“There have always been other architectures. But it is not just about the architecture; the ecosystem is the important part; the range of CPUs, the legacy software, the support tools. The offering is much more than an instruction set. RISC-V will be used but it’s not an existential threat to ARM.
Ronco pointed out that in the case of RISC-V that although the use of the instruction set is free a full-featured CPU based on RISC-V would still most likely be subject to licensing, royalties and maintenance costs. Also in the case of ARM you can bundle the CPU with lots of other IP cores.
I argued there was a time when ARM was the new Advanced RISC Machine and a contrast to x86 but since then ARM has gone through many architecture updates that carried the burden of providing backwards compatibility while also letting the instruction set become more complex. Surely RISC-V, which started in about 2010, with a clean design with small, fast, and low-power real-world implementations in mind has an advantage?
Ronco said: “I don’t feel we carry a lot of legacy. 64bit operation is still relatively new. I expect RISC-V to have a role in niches but there is a difference between RISC-V and ARM in scale and maturity.”
“You could build using RISC-V CPU and other IP cores, even other ARM IP cores, but why would you?” Ronco asked. “One use case for RISC-V is academia, where you publish everything and deeply,” he concluded
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