
Arteris expands Ncore cache coherent interconnect IP
Arteris is now supporting the ARMv9 cores and CHI-E interconnect with its latest cache coherent IP.
Version 3.6 of the Ncore interconnect IP developed by Arteris is aimed at low latency integration of hardware accelerators into a coherent domain with both ARM and RISC-V cores. The CHI-E support enables chiplet designs
Ncore can save SoC design teams upwards of 50 years of engineering effort per project compared to manually generated interconnect solutions says Andy Nightingale, VP of product management and marketing at Arteris.
The multi-protocol support allows integration of IPs connected to the same NoC fabric with CHI-E, CHI-B and ACE fully coherent agent interfaces and ACE-Lite IO-coherent interfaces. AXI is also supported for interfacing with sub-systems or devices without coherency requirements.
These can be used flexibly, with different bus structures used to access memory and registers in the cores. This is key to a more efficient interconnect, he says.
“Ncore may not be necessary across the system on chip so you use it where you need it,” he said. The IP has been pre-validated with the ARMv9 cores with bare metal and emulation testing and customers looking at 3nm SoC design and one or two evaluating 2nm process technology, while the majority of customers are on 5 and 7nm, he says.
He sees the IP as complementary to ARM’s Compute SubSystem (CSS) which also includes interconnect for chiplet designs. “I don’t see it as a problem,” said Nightingale. “The market is so huge there are customers that find CSS useful and others that want their own differentiation and build it themselves and they come to us.”
“We have worked with Arteris network-on-chip technology since 2010, using it in our advanced autonomous driving and driver-assistance technologies,” said Leonid Smolyansky, SVP SoC Architecture, Security & Safety at Mobileye.
The v3.6 IP is currently undergoing ISO26262 certification for functional safety which is expected in the next few weeks, says Nightingale.
“Our latest release of a production-proven Ncore marks an important milestone towards our ultimate cache coherent interconnect IP vision to connect any processor, using any protocol and topology,” said Charles Janac, president and CEO of Arteris.
The company says it has over 200 customers and 750 design starts with over 3.5bn chips shipped with the IP.
www.arteris.com/products/coherent-noc-ip/ncore/
