Arteris IP and Magillem partner on SoC architecture environment

Arteris IP and Magillem partner on SoC architecture environment

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By eeNews Europe

The first technical fruit of the partnership is the validation of full compliance of Arteris IP interconnects with the Magillem environment. Within a single environment, joint customers can now easily build a system-on-chip with multiple Ncore and FlexNoC instances. Using the Magillem front-end design environment, users can import Arteris FlexNoC non-coherent interconnects and Ncore cache coherent interconnects using the IP-XACT format. Detailed descriptions of the Arteris IP NoC instances imported into the Magillem environment can be used for full SoC assembly at the RTL and SystemC levels.

This integration eases the design of today’s highly complex artificial intelligence (AI) and autonomous driving SoCs, which are now bounded by the performance of on-chip interconnects rather than the performance of on-chip processors and hardware accelerators. The integration enables automatic checking and synchronization of system memory maps and speeds up the creation of derivative chip designs. Furthermore, use of machine-readable IEEE IP-XACT data allows for automated traceability throughout the development flow, which is important for compliance with functional safety standards like IEC 61508 and ISO 26262 for automotive systems.

Arteris IP –

Magillem –

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