Ashling supports cJTAG debug interface standard for Synopsys DesignWare ARC processor cores
cJTAG support requires a software update and a new revision (R1) of the Opella-XD’s Target Probe Assembly (TPA).
By adding support for the IEEE’s Compact JTAG standard in their Opella-XD Debug Probe for ARC processor cores, Ashling enables designers to use fewer pins to debug their SoCs containing ARC microprocessors, saving both power and cost.
Synopsys’ ARC processor IP includes the configurable ARC EM, ARC 600 and ARC 700 families of 32-bit processor cores, which enable SoC designers to implement a full range of embedded microprocessors optimized for their specific target application.
The Opella-XD datasheet is available on the Ashling website.
For more information, visit https://www.synopsys.com/arc
Visit Ashling Microsystems at www.ashling.com