Astera Labs expands PCIe 6.x test capabilities for AI servers

Astera Labs expands PCIe 6.x test capabilities for AI servers

Business news |
By Jean-Pierre Joosting

Astera Labs has expanded PCIe® 6.x testing capabilities in its Cloud-Scale Interop Lab to enable seamless interoperability between Aries 6 PCIe/CXL Smart DSP Retimers and a broad range of PCIe 6.x hosts and endpoints.

This paves the way for AI platform developers to design high-bandwidth, low-latency PCIe 6.x connectivity with confidence, reduce overall development time, and deploy at scale.

Thad Omura, Chief Business Officer, Astera Labs, said, “As AI systems continue to advance at a rapid pace, data center operators need to deploy increasingly complex systems on an accelerated timeline. Our intense focus on standards compliance and plug-and-play interoperability is foundational to why our widely deployed, field-tested Aries Retimer portfolio sets the gold standard for PCIe/CXL® connectivity. Expanding our Cloud-Scale Interop Lab test suite to support PCIe 6.x operation fast-tracks deployment for customers integrating Aries 6 — the industry’s lowest power PCIe 6.x/CXL 3.x Retimer — with solutions from our ecosystem partners.”

Higher bandwidth PCIe 6.x technology is required to maximize utilization of GPUs, CPUs, and AI accelerators to meet the performance demands of new AI workloads in hyperscale systems. However, this creates new connectivity issues with increases in speed, complexity, and scale. These challenges emphasize the need for extensive testing to ensure robust interoperability between the wide variety of PCIe 6.x components within an AI system deployed at cloud-scale.

For this reason, Aries 6 is put through a rigorous test suite to exercise the PCIe link with a series of loop tests over thousands of iterations and recreate end customers’ real-world system configurations with leading root complexes and over 50 endpoints in complex PCIe topologies.

Astera Labs has chosen Taiwan to launch its first Cloud-Scale Interop Lab outside of Silicon Valley given the region’s rich collection of leading technology design and manufacturing companies. This new interop lab location will facilitate closer collaboration with key ODM customers to test Aries 6 in complex PCIe topologies with a broad variety of hosts and end points interconnected over varying channel insertion loss budgets in real systems.

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles