Asynchronous SRAM with on-chip error-correcting code cuts soft errors

Asynchronous SRAM with on-chip error-correcting code cuts soft errors

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By eeNews Europe

The devices ensure data reliability in a wide variety of industrial, military, communication, data processing, medical, consumer and automotive applications. Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress’s new ssynchronous SRAMs performs all error correction functions inline, without user intervention, delivering lowest Soft Error Rate (SER) performance. The 16 Mb Fast Asynchronous SRAM achieves a 10-nsec access time and is pin-compatible with current Asynchronous SRAMs, enabling customers to boost system reliability while retaining board layout.

Cypress has also introduced a new Fast SRAM with PowerSnooze family that combines the 10-nsec access times of Fast SRAMs with low standby power comparable to that of the MoBL family. PowerSnooze is an additional power-saving Deep Sleep mode that achieves 12 µA (typical) deep-sleep current for a 16 Mb SRAM. The 16 Mb Fast SRAM with PowerSnooze also offers on-chip ECC.

The 16-Mbit Asynchronous SRAMs are offered in industry standard x8, x16 and x32 configurations. The devices operate at multiple voltages (1.8V, 3V, and 5V) over -40 to +85C (Industrial) and -40 to +125C (Automotive-E) temperature ranges.


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